Hewlett-Packard Development Company, L.p.

Advanced Micro Devices Corporation

Hewlett-Packard Company

Ati Technologies Ulc

Globalfoundries Inc.

Other

Intel Corporation

Samuel D Naffziger

John J Wuu

Steven Frederick Liepe

Christopher Allan Poirier

Timothy Charles Fischer

Donald R Weiss

Eric S Fetzer

Visvesh S Sathe

Stephen Victor Kosonocky

Milind S Bhagavat

John P Petry

Don D Josephson

Sriram Sambamurthy

Benjamin James Patella

Christopher Jonathan Bostak

Indrani Paul

Brett P Wilkerson

Sebastien Nussbaum

Leonardo De Paula Rosa Piga

Patrick J Shyvers

Aaron Joseph Grenat

Kaushik Mysore

Larry David Hewitt

Kevin Michael Lepak

Srikanth Arekapudi

Donald Charles Soltis, Jr

Kiran Bondalapati

Reid James Riedlinger

Ashish Jain

Jayen J Desai

Dana Glenn Lewis

Wonje Choi

Suresh B Periyacheri

Adam Neil Calder Clark

Sandhya Shyamasundar

Alexander J Branover

William Alexander Hughes

Russell J Schreiber

Eric M Rentschler

Michael J Osborn

Jonathan P Lotz

Eric R DeLano

Michael K Ciraula

Wayne Kever

John D Wanek

Benjamin D Bates

Shahram Ghahremani

Michael Mantor

Gregg Bernard Lesartre

Khaled Mammou

Vydhyanathan Kalyanasundharam

Benjamin Tsien

Rahul Kumar Agarwal

Douglas John Cutter

Kevin X Zhang

Derek L Knee

Gabor Sines

Mark Fowler

Skyler Jonathon Saleh

Lei Zhang

Ihab Amer

Spencer Montgomery Gold

Edward J McLellan

Robert H Miller, Jr

Haibo Liu

Mark M Leather

Edward A Harold

Glenn T Colon-Bonet

Jeffry D Yetter

Bradley Dean Winick

Maxat Touzelbaev

Barry Joseph Arnold

Arun Sundaresan Iyer

Michael J Austin

Michael Butler

Madhu Saravana Sibi Govindan

Michael L Golden

Andy Sung

Gia Tung Phan

Ali Akbar Merrikh

Baomin Liu

James Ignowski

Vasant K Palisetti

Kaushik Mazumdar

Krishna Sai Bernucho

Fabio Gulino

Dhirendra Partap Singh Rana

Charles Corey Pie

Sriram Sundaram

Christopher Eric Tressler

Gerard M Blair

Thomas Justin Sullivan

Donald M Kipp

Eric M Scott

Ashwin Chincholi

Umair B Cheema

Mom-Eng Ng

Preston J Renstrom

Rodolfo G Beraha

A graphics processing unit (GPU) of a processing system is partitioned into multiple dies (referred to as GPU chiplets) that are configurable to collectively function and interface with an application as a single GPU in a first mode and as multiple GPUs in a second mode. By dividing the GPU into multiple GPU chiplets, the processing system flexibly and cost-effectively configures an amount of active GPU physical resources based on an operating mode. In addition, a configurable number of GPU chiplets are assembled into a single GPU, such that multiple different GPUs having different numbers of GPU chiplets can be assembled using a small number of tape-outs and a multiple-die GPU can be constructed out of GPU chiplets that implement varying generations of technology.

Configurable multiple-die graphics processing unit

Platform power management includes boosting performance in a platform power boost mode or restricting performance to keep a power or temperature under a desired threshold in a platform power cap mode. Platform power management exploits the mutually exclusive nature of activities and the associated headroom created in a temperature and/or power budget of a server platform to boost performance of a particular component while also keeping temperature and/or power below a threshold or budget.

Platform power manager for rack level power and thermal constraints

Various semiconductor chip devices with stacked chips are disclosed. In one aspect, a semiconductor chip device is provided. The semiconductor chip device includes a first semiconductor chip that has a floor plan with a high heat producing area and a low heat producing area. At least one second semiconductor chip is stacked on the low heat producing area. The semiconductor chip device also includes means for transferring heat from the high heat producing area.

Arrangement and thermal management of 3D stacked dies

Refreshing displays using on-die cache, including: determining that a static display condition has been met; storing, in cache memory of a processor, first display data; and displaying the first display data from the cache memory.

Refreshing displays using on-die cache

A method for controlling a data processing system includes detecting a droop in a power supply voltage of a functional circuit of the data processing system greater than a programmable droop threshold. An operation of the data processing system is throttled according to a programmable step size, a programmable assertion time, and a programmable de-assertion time in response to detecting the droop.

Performance management during power supply voltage droop

A chiplet system includes a central processing unit (CPU) communicably coupled to a first GPU chiplet of a GPU chiplet array. The GPU chiplet array includes the first GPU chiplet communicably coupled to the CPU via a bus and a second GPU chiplet communicably coupled to the first GPU chiplet via a passive crosslink. The passive crosslink is a passive interposer die dedicated for inter-chiplet communications and partitions systems-on-a-chip (SoC) functionality into smaller functional chiplet groupings.

GPU chiplets using high bandwidth crosslinks

The low end operating voltage of an integrated circuit is adjusted. Oscillations are counted at a ring oscillator on the integrated circuit over a designated period of clock cycles. Based on the number of oscillations, a prediction model associated with a first set of device degradation data and a second set of static random-access memory (SRAM) low end operating voltage data is used to select a low end operating voltage limit for a processor on the integrated circuit. The low end operating voltage of the processor is set based on the selected low end operating voltage limit. These steps are repeated multiple times during operation of the processor. A method of testing integrated circuits to provide the data employed to produce the prediction model is also provided.

Mission mode Vmin prediction and calibration

A power management algorithm framework proposes: 1) a Quality-of-Service (QoS) metric for throughput-based workloads; 2) heuristics to differentiate between throughput and latency sensitive workloads; and 3) an algorithm that combines the heuristic and QoS metric to determine target frequency for minimizing idle time and improving power efficiency without any performance degradation. A management algorithm framework enables optimizing power efficiency in server-class throughput-based workloads while still providing desired performance for latency sensitive workloads. The power savings are achieved by identifying workloads in which one or more cores can be run at a lower frequency (and consequently lower power) without a significant negative performance impact.

Power efficiency optimization in throughput-based workloads

An integrated circuit includes first and second through-silicon via (TSV) circuits and a steering logic circuit. The first TSV circuit has a first TSV and a first multiplexer for selecting between a first TSV data signal received from the first TSV and a first local data signal for transmission to a first TSV output terminal. The second TSV circuit includes a second TSV and a second multiplexer for selecting between a second TSV data signal received from the second TSV and the first local data signal for transmission to a second TSV output terminal. The steering logic circuit controls the first multiplexer to select the first local data signal and the second multiplexer to select the second TSV data signal in a first mode, and the first multiplexer to select the first TSV data signal and the second multiplexer to select the first local data signal in a second mode.

Flexibile interfaces using through-silicon via technology

Systems, apparatuses and methods of adaptively controlling a cache operating voltage are provided that comprise receiving indications of a plurality of cache usage amounts. Each cache usage amount corresponds to an amount of data to be accessed in a cache by one of a plurality of portions of a data processing application. The plurality of cache usage amounts are determining based on the received indications of the plurality of cache usage amounts. A voltage level applied to the cache is adaptively controlled based on one or more of the plurality of determined cache usage amounts. Memory access to the cache is controlled to be directed to a non-failing portion of the cache at the applied voltage level.

Adaptive resizable cache/LCM for improved power

Growing community of inventors

Ft. Collins, CO, United States of America

Samuel D Naffziger