Taiwan Semiconductor Manufacturing Comp. Ltd.

National Taiwan University

Macronix International Co., Ltd.

National Yang Ming Chiao Tung University

Samuel C Pan

Chee-Wee Liu

Jenn-Gwo Hwu

Hao-Hsiung Lin

Si-Chen Lee

Shih-Yen Lin

I-Hsieh Wong

Miin-Jang Chen

Pin-Shiang Chen

Che-Wei Yang

Fang-Liang Lu

Chi-Wen Liu

Hung-Chih Chang

Kuan-Chao Chen

Chao-Hsiung Wang

Tao-Cheng Lu

Tuo-Hung Hou

Chien-Shun Liao

Chee Wee Liu

Hung-Yu Yeh

Wei-Cheng Tian

Chung-Yen Hsieh

Wen-Jer Tsai

Chin-Yi Huang

Yun Shen Chang

Chao-Hsin Chien

Sheng-Ting Fan

Cheewee Liu

Chen-Han Chou

Kuan-Hao Tseng

Hung-Hsiang Cheng

Shih-Ya Lin

Pang-Shiuan Liu

Chang-Feng Yan

Yu-Ming Lin

Chih-Chieh Yeh

Cheng-Ting Chung

Tso-Hung Fan

Min-Hung Lee

Kuen-Yu Tsai

Chung-En Tsai

Chao-Hsin Wu

Meng-Yu Lin

Jhih-Yang Yan

Huang-Siang Lan

Der-Chuan Lai

Hsun-Ming Chang

Da-Zhi Zhang

Ching-Yu Chang

Chun-Jung Lin

Pin Chia Su

James Juen Hsu

Steve S Chung

Nan-Hsin Tseng

Wei-Pin Changchien

Yu-Cheng Shen

Chia-Hsing Chen

Chun-Pei Wu

Ji-Jan Chen

Chih-I Wu

Ta-Hui Wang

Chong-Rong Wu

E-Ray Hsieh

Wen-Bin Tsai

Yen-Ling Liu

Ming-Long Fan

Pi-Ho Hu

CheeWee Liu

Cheng-Heng Kao

Yu-Bin Zhao

Yin-Nien Chen

Huei-Huang Chen

Xian-Rui Chang

Yi-Jen Huang

Ching-Te (Kent) Chuang

Minnie Hsiung

Chih-Jen Huang

Huei Huarng Chen

Yu-Hung Liao

Shang-Yi Liu

Tsung-Chin Cheng

Po-Shuan Yang

A semiconductor device includes a first layer that includes a first semiconductor material disposed on a semiconductor substrate, and a second layer of a second semiconductor material disposed on the first layer. The semiconductor substrate includes Si. The first semiconductor material and the second semiconductor material are different. The second semiconductor material is formed of an alloy including a first element and Sn. A surface region of an end portion of the second layer at both ends of the second layer has a higher concentration of Sn than an internal region of the end portion of the second layer. The surface region surrounds the internal region.

Semiconductor device and manufacturing method thereof

A method for controlling Schottky barrier height in a semiconductor device includes forming an alloy layer including at least a first element and a second element on a first surface of a semiconductor substrate. The semiconductor substrate is a first element-based semiconductor substrate, and the first element and the second element are Group IV elements. A first thermal anneal of the alloy layer and the first element-based substrate is performed. The first thermal anneal causes the second element in the alloy layer to migrate towards a surface of the alloy layer. A Schottky contact layer is formed on the alloy layer after the first thermal anneal.

Method for reducing Schottky barrier height and semiconductor device with reduced Schottky barrier height

A metal-insulator-semiconductor-insulator-metal (MISIM) device includes a semiconductor layer, an insulating layer disposed over an upper surface of the semiconductor layer, a back electrode disposed over a lower surface of the semiconductor layer opposing the upper surface, and first and second electrodes disposed over the insulating layer and spaced-apart from each other.

Metal-insulator-semiconductor-insulator-metal (MISIM) device, method of operation, and memory device including the same

A semiconductor memory device includes a transistor having a gate, a source and a drain and a metal-insulator-semiconductor (MIS) structure. The transistor and the MIS structure are disposed on a common substrate. The MIS structure includes a dielectric layer disposed on a semiconductor region, and an electrode electrically disposed on the dielectric layer and coupled to the drain of the transistor. The electrode includes a bulk portion and a high-resistance portion, both disposed on the dielectric layer. The high-resistance portion has a resistance value in a range from 1.0&#xd7;10&#x3a9;cm to 1.0&#xd7;10&#x3a9;cm or a sheet resistance in a range from 1.0&#xd7;10&#x3a9;/&#x25a1; to 1.0&#xd7;10&#x3a9;/&#x25a1;.

Semiconductor memory device

A semiconductor device includes a semiconductor fin protruding from a substrate, a gate electrode over the semiconductor fin, a gate insulating layer between the semiconductor fin and the gate electrode, source and drain regions disposed on opposite sides of the semiconductor fin, a first stressor formed in a region between the source and drain regions. The first stressor including one material selected from the group consisting of He, Ne, and Ga.

Method for forming stressor, semiconductor device having stressor, and method for forming the same

A method of fabricating a semiconductor device having two dimensional (2D) lateral hetero-structures includes forming alternating regions of a first metal dichalcogenide film and a second metal dichalcogenide film extending along a surface of a first substrate. The first metal dichalcogenide and the second metal dichalcogenide films are different metal dichalcogenides. Each second metal dichalcogenide film region is bordered on opposing lateral sides by a region of the first metal dichalcogenide film, as seen in cross-sectional view.

2D crystal hetero-structures and manufacturing methods thereof

A device includes a phosphide-containing structure, a dopant source layer and a conductive contact. The phosphide-containing structure has a first chemical element in a compound with phosphorus. The dopant source layer is over the phosphide-containing structure and has a second chemical element the same as the first chemical element. The conductive contact is over the dopant source layer.

Device with doped phosphorene and method for doping phosphorene

A semiconductor device includes a first layer of a first semiconductor material disposed on a semiconductor substrate and a second layer of a second semiconductor material disposed on the first layer. The second semiconductor material is formed of an alloy that includes a first element and a second element. The first semiconductor material and the second semiconductor material are different. A gate structure is disposed on a first portion of the second layer. A surface region of a second portion of the second layer not covered by the gate structure has a higher concentration of the second element than an internal region of the second portion of the second layer, and the surface region surrounds the internal region.

A semiconductor device including a field effect transistor (FET) device includes a substrate and a channel structure formed of a two-dimensional (D) material over the substrate. Source and drain contacts are formed partially over theD material. A first dielectric layer is formed at least partially over the channel structure and at least partially over the source and drain contacts. The first dielectric layer is configured to trap charge carriers. A second dielectric layer is formed over the first dielectric layer, and a gate electrode is formed over the second dielectric layer.

Impact ionization semiconductor device and manufacturing method thereof

A method of fabricating a semiconductor device includes plasma etching a portion of a plurality of metal dichalcogenide films comprising a compound of a metal and a chalcogen disposed on a substrate by applying a plasma to the plurality of metal dichalcogenide films. After plasma etching, a chalcogen is applied to remaining portions of the plurality of metal dichalcogenide films to repair damage to the remaining portions of the plurality of metal dichalcogenide films from the plasma etching. The chalcogen is S, Se, or Te.

Method of forming a semiconductor device using layered etching and repairing of damaged portions

A method for forming an antifuse on a substrate is provided, which comprises: forming a first conductive material on the substrate; placing the first conductive material in an electrolytic solution; performing anodic oxidation on the first conductive material to form a nanowire made of the first conductive material and surrounded by a first dielectric material formed during the anodic oxidation and to form the antifuse on the nanowire; and forming a second conductive material on the antifuse to sandwich the antifuse between the first conductive material and the second conductive material.

Antifuse array and method of forming antifuse using anodic oxidation

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Hsinchu, Taiwan

Samuel C Pan