Applied Materials, Inc.

Xilinx, Inc.

Samuel Broydo

Mehul B Naik

Dan Maydan

Lawrence Camest West

Khue Duong

Sheau-suey Li

Randy T Ong

Claes Björkman

Manoocher Birang

Shamouil Shamouilian

Suketu Arun Parikh

Claes H Bjorkman

H Peter W Hey

An article of manufacture comprising an optical-ready substrate made of a first semiconductor layer, an insulating layer on top of the first semiconductor layer, and a second semiconductor layer on top of the insulating layer, wherein the second semiconductor layer has a top surface and is laterally divided into two regions including a first region and a second region, the top surface of the first region being of a quality that is sufficient to permit microelectronic circuitry to be formed therein and the second region including an optical signal distribution circuit formed therein, the optical signal distribution circuit made up of interconnected semiconductor photonic elements and designed to provide signals to the microelectronic circuit to be fabricated in the first region of the second semiconductor layer.

Optical ready substrates

An article of manufacture comprising an optical ready substrate made of a first semiconductor layer, an insulating layer on top of the first semiconductor layer, and a second semiconductor layer on top of the insulating layer, wherein the second semiconductor layer has a top surface and is laterally divided into two regions including a first region and a second region, the top surface of the first region being of a quality that is sufficient to permit microelectronic circuitry to be formed therein and the second region including an optical signal distribution circuit formed therein, the optical signal distribution circuit made up of interconnected semiconductor photonic elements and designed to provide signals to the microelectronic circuit to be fabricated in the first region of the second semiconductor layer.

An optical ready substrate made at least in part of a first semiconductor material and having a front side and a backside, the front side having a top surface that is of sufficient quality to permit microelectronic circuitry to be fabricated thereon using semiconductor fabrication processing techniques. The optical ready substrate includes an optical signal distribution circuit fabricated on the front side of the substrate in a first layer region beneath the top surface of the substrate. The optical signal distribution circuit is made up of interconnected semiconductor photonic elements and designed to provide signals to the microelectronic circuitry to be fabricated thereon.

Optical ready wafers

A dual damascene technique that forms a complete via in a single step. Specifically, the method deposits a first insulator layer upon a substrate, an etch stop layer over the first insulator layer, and a second insulator layer atop the etch stop layer. A via mask is then formed by applying a photoresist which is developed and patterned according to the locations of the dimensions of the ultimate via or vias. Thereafter, the first insulator layer, the etch stop layer and the second insulator layer may be etched in a single step, for example, using a reactive ion etch. The hole that is formed through these three layers has the diameter of the ultimate via. Thereafter, a trench is masked and etched into the second insulator layer. The trench etch is stopped by the etch stop layer. The via and trench are metallized to form an interconnect structure. The technique can be repeated to create a multi-level interconnect structure.

Method of producing an interconnect structure for an integrated circuit

The present invention provides integrated circuit fabrication methods and devices wherein dual damascene structures ( and ) are formed in consecutive dielectric layers ( and ) having dissimilar etching characteristics. The present invention also provides for such methods and devices wherein these dielectric layers have different dielectric constants. Additional embodiments of the present invention include the use of single layer masks, such as silicon-based photosensitive materials which form a hard mask ( ) upon exposure to radiation. In additional embodiments, manufacturing systems ( ) are provided for fabricating IC structures. These systems include a controller ( ) which is adapted for interacting with a plurality of fabrication stations ( and ).

Interconnect line formed by dual damascene using dielectric layers having dissimilar etching characteristics

An ESD protection circuit combines a split bipolar transistor with a transistor layout which exhibits very high tolerance to ESD events. The split bipolar transistor divides current among many segments and prevents the current hogging which often causes an ESD failure. Several splitting structures are disclosed, each combining a resistor in series with each segment to distribute current evenly. The transistor takes advantage of the snap-back effect to increase current carrying capacity. Layout positions metal contacts away from regions of highest energy dissipation. Layout also allows high currents to be dissipated through ESD protection structures and not through circuit devices such as output drivers or through parasitic bipolar transistors not designed for high current. Sharp changes in electron density are avoided by the use of high-diffusing phosphorus in N-regions implanted to both lightly and heavily doped levels. Critical corners are rounded rather than sharp. Certain P-type channel stop implants are positioned away from nearby N-regions to increase breakdown voltage.

ESD protection circuit

A multi-electrode electrostatic chuck (20) for holding a substrate (42) such as a silicon wafer during processing is described. The electrostatic chuck (20) comprises (i) a first electrode (22), (ii) a second electrode (24), and (iii) an insulator (26) having a lower portion (26a), a middle portion (26b) and an upper portion (26c). The lower portion (26a) of the insulator (26) is below the first electrode (22) and has a bottom surface (28) suitable for resting the chuck (20) on a support (44) in a process chamber (41). The middle portion (26b) of the insulator (26) lies between the first and second electrodes (22), (24). The upper portion (26c) of the insulator (26) is on the second electrode (24), and has a top surface (30) suitable for holding a substrate (42). The first and second electrodes (22, 24) can have a unipolar or bipolar configurations. In operation, the chuck (20) is placed on a support (44) in a process chamber (41) so that the bottom surface (28) of the chuck (20) rests on the support (44). A substrate (42) is placed on the top surface (30) of the chuck (20). When the first electrode (22) of the chuck (20) is electrically biased with respect to the support (44), a first electrostatic force holds the chuck (20) onto the support (44). When the second electrode (24) of the chuck (20) is electrically biased with respect to the substrate (42) placed on the chuck (20), a second electrostatic force holds the substrate (42) to the chuck (20).

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Los Altos Hills, CA, United States of America

Samuel Broydo