Micron Technology Incorporated

Sampath K Ratnam

Kishore Kumar Muchherla

Peter Sean Feeley

Ashutosh Malshe

Vamsi Pavan Rayaprolu

Harish Reddy Singidi

Sivagnanam Parthasarathy

Michael G Miller

Mustafa Nazmi Kaynak

Renato C Padilla

Shane G Nowell

Gary F Besinga

Christopher S Hale

Gianni Stephen Alsasua

Renato Padilla, Jr

Jiangang Wu

Kevin Roy Brandt

Karl David Schuh

Xiangang Luo

Preston Allen Thomson

Yun Li

Daniel J Hubbard

Jung Sheng Hoei

Qisong Lin

Devin M Batutis

Patrick Robert Khayat

Christopher M Smitchger

Tawalin Opastrakoon

Kulachet Tanpairoj

Marc S Hamilton

Violante Moschiano

Jianmin Huang

Ting Luo

Satish K Yanamanamanda

Scott Anthony Stoller

Larry Joseph Koudele

Walter Di-Francesco

James Fitzpatrick

Michael Sheperek

Dung Viet Nguyen

Jie Zhou

Cory M Steinmetz

Zixiang Loh

Troy A Manning

Akira Goda

Mark Alan Helm

Shuhui Chen

Troy D Larsen

Xu Zhang

Giuseppina Puzzilli

Todd A Marquart

Doyle W Rivers

Saeed Sharifi Tehrani

Martin L Culley

Roland J Awusie

Yifen Liu

Nagendra Prasad Ganesh Rao

Sead Zildzic

Pushpa Seetamraju

Shantilal Doru

Hong Lu

Guang Chang Ye

Shao Chun Shi

Abolfazl Rashwand

Yingda Dong

Sean Stephen Eilert

Ching-Huang Lu

Jun Wan

Luca Bert

Deping He

Steven Michael Kientz

David Scott Ebsen

William C Filipiak

HyungSeok Kim

Brent Byron

John Zhang

Michael G McNeeley

Thomas Herbert Lentz

Larry K Koudele

Asheesh Kwatra

Sean Brasfield

Control logic in a memory device executes a programming operation to program a memory cell of a set of memory cells to a programming level. A first erase sub-operation is executed to erase the memory cell to a first threshold voltage level, the first erase sub-operation including applying, to the memory cell, a first erase pulse having a first erase voltage level. A second erase sub-operation is executed to erase the memory cell to a second threshold voltage level, the second erase sub-operation including applying, to the memory cell, a second erase pulse having a second erase voltage level, where the first erase voltage level of the first erase pulse is lower than the second erase voltage level of the second erase pulse.

Multi-stage erase operation of memory cells in a memory sub-system

Various embodiments provide for processing write requests on a memory system based on queue identifiers associated with the write requests. In particular, input data streams can be received and stored by submission queues of a memory system, and write requests in the input data streams can be separated and processed based on queue identifiers associated with the submission queues using an inline approach for writing data on the memory system, an offline approach for writing data on the memory system, or both.

Processing write requests based on queue identifier

A processing device in a memory sub-system detects an occurrence of a data integrity check trigger event and, responsive to the occurrence of the data integrity check trigger event, identifies a memory die of a plurality of memory dies. The processing device further associates each segment of the identified memory die with a respective group of a plurality of groups, each group representing one or more of a plurality of error mechanisms, and determines one or more respective adaptive scan frequencies for the identified memory die based on statistics of the segments associated with each respective group.

Adaptive integrity scan rates in a memory sub-system based on block health metrics

Respective error handling (EH) flags can be set based at least in part on media management data of a memory device. Whether any of the EH flags are set can be determined. In response to determining that at least one of the EH flags is set, a subset of a plurality of operations of an EH flow associated with the set EH flags can be performed.

Error handling

Aspects of the present disclosure configure a memory sub-system controller to allow a host to deallocate data prior to folding operations. The controller generates an instruction to fold data stored in an individual portion of the set of memory components. The controller, prior to executing the instruction to fold the data stored in the individual portion of the set of memory components, transmits a communication to a host indicative of the instruction to fold the data stored in the individual portion. The controller conditions execution of the instruction to fold the data stored in the individual portion of the set of memory components based on transmission of the communication to the host.

Preemptively warning host of background folding

A method includes identifying, by a processing device, a common pool of blocks comprising a first plurality of blocks allocated to system data and a second plurality of blocks allocated to user data; determining whether user data has been written to the second plurality of blocks within a threshold period of time; and responsive to determining that the user data has not been written to the second plurality of blocks within the threshold period of time, allocating a block from the second plurality of blocks to the first plurality of blocks.

Using a common pool of blocks for user data and a system data structure

Described are systems and methods for memory read threshold tracking based on memory device-originated metrics characterizing voltage distributions. An example memory device includes: a memory array having a plurality of memory cells and a controller coupled to the memory array. The controller is to perform operations including: receiving a first value of a metric characterizing threshold voltage distributions of a subset of a set of the plurality of memory cells; determining a first voltage threshold adjustment value; receiving a second value of the metric; determining a second voltage threshold adjustment value; and applying the second voltage threshold adjustment value for reading the set of the plurality of memory cells.

Memory read voltage threshold tracking based on memory device-originated metrics characterizing voltage distributions

An amount of voltage shift is determined for one or more memory cells of a block family based on an initial reference value pertaining to the one or more memory cells and a subsequent reference value pertaining to the one or more memory cells. The block family is associated with a first voltage bin or a second voltage bin based on the determined amount of voltage shift. The first voltage bin is associated with a first voltage offset and the second voltage bin is associated with a second voltage offset.

Voltage bin calibration based on a voltage distribution reference voltage

A first host data item and a second host data item are received. The first host data item is stored in a first page of a first logical unit of a memory device, where the first page is one of a plurality of pages associated with redundancy metadata. A second page a second page of a second logical unit of the memory device is identified, where the second page is one of the plurality of pages associated with the redundancy metadata, and the first page and the second page are associated with different wordlines of the memory device. The second host data item is stored in the second page of the second logical unit of the memory device. The first page and the second page can be associated with a fault tolerant stripe that includes the redundancy metadata.

Diagonal page mapping in memory systems

Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations comprising performing a data integrity check on a source set of memory cells, configured to store a first number of bits per memory cell, to obtain a data integrity metric value; responsive to determining that the data integrity metric value satisfies the threshold criterion, performing an error handling operation on the data stored on the source set of memory cells to generate corrected data; and causing the memory device to copy data the corrected data to a destination set of memory cells of the memory device, wherein the destination set of memory cells are configured to store a second number of bits per memory cell, wherein the second number of bits per memory cells is greater than the first number of bits per memory cell.

Memory compaction management in memory devices

In some implementations, a controller of a memory device may obtain a first metric associated with a memory of the memory device using a first memory read configuration. The controller may apply a function to the first metric to obtain a second memory read configuration. The controller may obtain a second metric associated with the memory using the second memory read configuration. The controller may filter the first metric and the second metric to obtain a first filtered metric and a second filtered metric. The controller may provide the first filtered metric and the second filtered metric to a memory management process executing on the controller. The controller may perform an action based on an output of the memory management process, wherein the output is based on the first filtered metric and the second filtered metric.

Filtering metrics associated with memory

Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including detecting a read error with respect to data residing in a first block of the memory device, wherein the first block is associated with a voltage offset bin; determining a most recently performed error-handling operation performed on a second block associated with the voltage offset bin; and performing the error-handling to recover the data.

Managing error-handling flows in memory devices

A memory system includes a memory array having a plurality of memory cells; and a controller coupled to the memory array, the controller configured to: designate a storage mode for a target set of memory cells based on valid data in a source block, wherein the target set of memory cells are configured with a capacity to store up to a maximum number of bits per cell, and the storage mode is for dynamically configuring the target set of memory cells in as cache memory that stores a number of bits less per cell than the corresponding maximum capacity.

Memory device with dynamic cache management

An example method of performing read operation comprises: receiving a read request with respect to a set of memory cells of a memory device; determining a value of a media endurance metric of the set of memory cells; determining a programing temperature associated with the set of memory cells; determining a current operating temperature of the memory device; determining a voltage adjustment value based on the value of the media endurance metric, the programming temperature, and the current operating temperature; adjusting, by the voltage adjustment value, a bitline voltage applied to a bitline associated with the set of memory cells; and performing, using the adjusted bitline voltage, a read operation with respect to the set of memory cells.

Cross-temperature compensation based on media endurance in memory devices

Memory devices are disclosed. A memory device may include dynamic cache, static cache, and a memory controller. The memory controller may be configured to disable the static cache responsive to a number of program/erase (PE) cycles consumed by the static cache being greater than an endurance of the static cache. The memory controller may also be configured to disable the dynamic cache responsive to a number of PE cycles consumed by the dynamic cache being greater than an endurance of the dynamic cache. Associated methods and systems are also disclosed.

Memory devices and systems including static and dynamic caches, and related methods

Growing community of inventors

Boise, ID, United States of America

Sampath K Ratnam