Alliedsignal Inc.

Intersil Corporation

Sampat S Shekhawat

John J Tumpey

Robert C Eckenfelder

John M Coronati

Gayton L Silvestro

Raymond Walter Borden

Anup Bhalla

William M Scherzinger

Alfred W Wohlberg

Eli Liebermann

James C Widdis

Kapal Gandikota

David Hodge

Nick Suttora

Jon Gladish

John J Brogle

An IGBT gate driver circuit includes means for detecting when the collector-to-emitter voltage (Vce) of a turned-on IGBT, intended to be operated in the saturation region, increases above a preset level, indicative of a fault condition, such as a short circuit. In response to such an increase in the Vce of a turned on IGBT, the IGBT is turned-off in two steps. First, the turn-on gate drive is decreased to a level that is still above the threshold (turn-on) voltage of the IGBT in order to decrease the current flowing through the IGBT and hence, the peak power dissipation. This decrease in the current through the IGBT and the peak power dissipation increases the length of time the IGBT can withstand a fault condition such as a short circuit. Then, after decreasing the gate drive to the IGBT, the gate drive is gradually decreased until the IGBT is completely turned off.

IGBT gate drive circuit with short circuit protection

A power module includes a semiconductor substrate and spaced power transistor circuits formed in the substrate, each having respective anode and cathode portions. A power module housing substantially encloses the substrate. Flexible cathode straps and flexible anode straps are connected to the respective anode and cathode portions and extend out of the power module housing spaced from each other. At least two anode straps and cathode straps fold over at least a portion of the power module housing to overlap each other and form phase straps. The remaining cathode and anode straps fold over at least a portion of the power module housing such that respective cathode and anode straps overlap each other, thereby lowering inductance and reducing voltage overshoots at turn off.

Power module with lowered inductance and reduced voltage overshoots

A control scheme for a wound rotor synchronous generator whereby feedback signals corresponding to the exciter field current and the generator output voltage potential combine together to control the generator output voltage in such a way that at lower generator speeds and lower load requirements, exciter field current saturation is eliminated by reducing generator output voltage. The generator control scheme includes a circuit for sensing exciter field current in logic cooperation with a circuit for sensing generator voltage. Both sensing circuits regulate the current applied to the exciter field which corresponds to the rectified current applied to the field windings of the power generator. During steady state operations the generator output voltage is regulated using the generator output voltage as a feedback signal. At lower speeds and reduced loads and as the exciter field current approaches the saturation point, the generator output voltage is regulated using the exciter field current as a feedback signal.

Voltage/current controlled voltage regulator to eliminate exciter field

An aircraft engine start system eliminates the need of a separate exciter field inverter by rearranging the exciter field windings and by utilizing external AC power. The aircraft engine is started by external AC power and once the engine has started, the engine can supply power back to a variable frequency AC bus as well as back to a constant frequency AC bus through the start/generator converter mode.

Aircraft engine electric start system without a separate exciter field

A plurality of power semiconductor switching devices are included in a circuit module in a pattern whereby interconnecting lead lengths are minimized to provide improved circuit characteristics and to insure uniform current sharing when said devices are paralleled during switch-on, switch-off and steady state conditions.

Interconnection arrangement for power semiconductor switching devices

This invention provides for an enabling circuit that ensures a positive turn-on of semiconductor switches configured for the generation of a synthesized waveform, thereby eliminating misfiring of the switches due to electronic noise or logic malfunction. The circuit is configured to separately compare a sample waveform with a positive reference voltage and a negative reference voltage. The two results are directed to separate logic AND gates which have respective control signal inputs that regulate the formation of the positive and negative portion of a synthesized waveform. The output signals from the two AND gates connect to logic means to control the firing of the semiconductor switches.

Shoot-through protection circuit for improved stability in a

A multi-step, alternating current power supply that provides for a failed-operation redundancy safety system that compensates for a short-circuited power switch and maintains an AC regulated output voltage without introducing undesirable harmonic components. The firing and logic controller 33 senses a short-circuited power switch 46 within an inverter bridge 32 and disables all complementary power switches 48 within the faulted bridge and enables the remaining power switches 50 in the faulted bridge. The firing sequence is adjusted for the remaining healthy power switches 52 by increasing the phase shift of the individual waveforms 54. The generator voltage is increased as required to maintain the desired AC voltage output level 56.

Fault compensating multi-step wave inverter

A two-sided hermetically sealed package of a metal matrix composite material includes a heat sink and integral cooling fins on each of the two sides which are totally enclosed to retain cooling fluid. Power semiconductors are mounted on ceramic substrates having metallic conductors mounted on both sides thereof. The substrates are mounted to the heat sinks. Cooling is provided by the passage of cooling fluid into one end of the enclosed fins, over the fins and out the other end. The metal matrix composite material and the ceramic are thermally matched and the package is provided with a minimum number of thermal interfaces.

Packaging arrangement for power semiconductor devices

A proportional base drive circuit for a power transistor. A first MOSFET, when enabled by an ON pulse, initially supplies the base drive current from a power supply to the base of the power transistor. The resulting current flow through the transistor to a load causes a proportional current to be induced in a current transformer. The induced current is supplied to the base of the power transistor through the first MOSFET. When an OFF pulse is applied, the first MOSFET is disabled and supplies no current to the base of the transistor. At the same time a second MOSFET causes the base-emitter junction of the power transistor to be negatively biased, thereby quickly switching the power transistor off.

Proportional base drive circuit

A snubber circuit for a neutral clamped power inverter. The power inverter includes power transistors, a current sensor at the inverter output and a neutral clamping circuit connected between the inverter output and a neutral point in a DC power source which supplies the inverter. A controller circuit is connected to the current sensor, to the power transistors and to the neutral clamping circuit to selectively enable and disable the power transistors and the neutral clamping circuit in accordance with the inverter operation and current direction at the inverter output to minimize current transients at a load. An active snubber arrangement is provided to minimize snubber losses when the power transistors are inactive during alternate positive and negative half-cycles of operation.

Power inverter snubber circuit

A sine wave synthesis controller circuit intended to be utilized in conjunction with a digitally-controlled neutral-point clamped inverter to produce a sinusoidal waveform from a direct current source. The controller circuit is configured so that it provides separate positive and negative control signals to the neutral-point clamped inverter's logic controller. These signals direct the modulation a sinusoidal waveform in response to a reference sine wave, the instantaneous voltage output by the neutral-point clamped inverter, as well as positive and negative reference voltages input to the controller.

Sine wave synthesis controller circuit for use with a neutral-point

A power inverter having a neutral clamping circuit which is controlled for low harmonic output. The power inverter includes power transistors, a current sensor at the inverter output and a neutral clamping circuit connected between the inverter output and a neutral point in a DC power source which supplies the inverter. A controller circuit is connected to the current sensor, to the power transistors and to the neutral clamping circuit to selectively enable and disable the power transistors in the neutral clamping circuit in accordance with the inverter operation and current direction at the inverter output to minimize current transients at the load.

Growing community of inventors

Mountaintop, PA, United States of America

Sampat S Shekhawat