Linear Technology Corporation

Sammy S Lum

William C Rempfer

A simple, low-cost circuit and method for line zing parasitic capacitances of transistor junctions, independent of the process technology employed, are provided. In the preferred embodiment, the parasitic capacitance of a transistor in a track and hold circuit is linearized by providing a pair of diodes that act inversely to the parasitic diodes formed within the integrated circuit during normal tracking operations. Without the diodes of the present invention, the varying input signals cause the parasitic capacitance to vary, thereby causing harmonic distortion in the track and hold circuit. An alternate embodiment of the present invention is also provided in which a second complementary transistor is provided. The inclusion of the complementary transistor results in a second set of parasitic capacitances that are substantially opposite the parasitic capacitances of the track and hold transistor. Additionally, depending on the ratios of the various components, the techniques of the two embodiments may be, combined, such that additional diode may be added even if the complementary transistor technique is utilized.

Circuits and methods for compensating non-linear capacitances to

Power shutdown of an integrated circuit such as a data acquisition system is implemented by software command. In one embodiment of a data acquisition system, an 8 bit data input word for configuring the operation of the data acquisition system includes two word length bits which define the length of data output words. One combination of the word length bits is utilized to command power shutdown. A decoder within the integrated circuit identifies the power shutdown command and generates a power shutdown signal (PS) to minimize power consumption when the circuit is not in operation.

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Alameda, CA, United States of America

Sammy S Lum