Lockheed Electronics Co., Inc.

Sammy S Henig

A refresh circuit for a dynamic semiconductor memory wherein each access to the main semiconductor memory for the storage or retrieval of information is detected and recorded in an auxiliary memory. During each memory access, the memory row being accessed is automatically refreshed as part of the storage or retrieval process. In accordance with the invention, the auxiliary memory is examined prior to the commencement of a refresh cycle and if a particular row in the main memory has been accessed during the current refresh cycle, that row is not refreshed but is skipped until the next refresh cycle, at which time the need for a refresh signal is again determined.

Refresh cycle minimizer in a dynamic semiconductor memory

Multiple usage requests for a common resource, such as a memory system, are given usage priorities by a multiple request arbitration circuit. Priority is given to a predetermined one of the input signals occurring prior to any one of the remaining input signals and priority is also given to the one input signal if it occurs within a predetermined interval subsequent to any one of the remaining input signals. The circuit also provides for the suppression of voltage transients which may occur upon the essentially simultaneous occurrence of more than one input signal and the circuit also provides a faster access time for input signals other than the predetermined one of the input signals.

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Clifton, NJ, United States of America

Sammy S Henig