Altera Corporation

Cypress Semiconductor Corporation

Sammy S Cheung

Kar Keng Chua

Hee Kong Phoon

Kim Pin Tan

Wei Lian Goay

Rakesh H Patel

Tony K Ngai

Sergey Yuryevich Shumarayev

Boon Jin Ang

Vinson Chan

Timothy M Lacey

Henry Y Lui

Ben Y Sheen

Choong Kit Wong

John D Lam

A Majid Farmanfarmaian

Simon John Lovett

Mark William Rouse

Providing ASIC equivalents of FPGAs is facilitated and made more efficient and economical by using an ASIC architecture including a plurality of so-called hybrid logic elements ('HLEs'), each of which can provide a portion of the full functionality of an FPGA logic element ('LE'). The functionality of each FPGA LE implementing a user's logic design can be mapped to one or more HLEs without re-synthesis of the user's logic. Only as many HLEs as are necessary are used to perform the functions of each LE. The one-for-one equivalence between each LE and either (1) one HLE or (2) a group of HLEs facilitates mapping (without re-synthesis) in either direction between FPGA and ASIC designs.

Application-specific integrated circuit equivalents of programmable logic and associated methods

A test platform is configured to test a mult-die package having at a first die and a second die. The test platform includes a first lead that is connected to the VCC input on the first die. The test platform also includes a second lead that is connected to VCCIO input on the second die. The VCC input on the second die is connected to ground. The I/O pin of the second die can then be tri-stated using a control circuit disposed between the pre-driver and the driver of the I/O buffer.

Isolation testing scheme for multi-die packages

A clock divider is described. The clock divider includes: a positive edge triggered state machine having a first input for receiving a first input signal and a first output for providing a first output signal; a negative edge triggered state machine having a second input for receiving a second input signal and a second output for providing a second output signal; and a first combination logic coupled to the positive edge triggered state machine and the negative edge triggered state machine, the first combination logic having a third input for receiving third input signals and a third output for providing a third output signal, where (1) at least one of the first input signal and the second input signal includes an input clock signal having an input clock signal period, (2) the third input signals include the first output signal and the second output signal, and (3) the third output includes an output clock signal having an output clock signal period, where the output clock signal period is a multiple of the input clock signal period.

Clock divider using positive and negative edge triggered state machines

Techniques for providing high-performance interconnect for integrated circuits will improve overall integrated circuit performance. These techniques include arranging, laying out, and fabricating the signal conductors (e.g.,,) so the parasitic coupling capacitances (e.g.,,) are minimized and parasitic resistance is reduced. The techniques will minimize effects of crosstalk noise between the conductors, and thus improve overall integrated circuit performance.

High-performance interconnect

An output buffer has internal circuitry connected between an input node and an output node. The internal circuitry includes a quiet voltage supply connected to a first set of transistors of the internal circuitry and a noisy voltage supply connected to a second set of transistors of the internal circuitry. The noisy voltage supply is at a voltage level higher than the quiet voltage supply. The first set of transistors and the second set of transistors provide isolation between the noisy voltage supply and the quiet voltage supply. The first set of transistors and the second set of transistors also provide complete digital high and low internal signal levels by using at least one transistor operative to supplement the complete shut-off and turn-on of transistors of the first set of transistors and the second set of transistors. The output buffer also features a ground bounce circuit, a slew rate control circuit, a transition accelerator circuit, a Personal Computer Interface (PCI) compatibility circuit, and a PCI control circuit.

High performance output buffer

A novel synchronous latching scheme is disclosed for use in connection with an EPROM device having a limited number of pins for control signals. A negative edge-triggered d-type master-slave latch having a D-input, and a clock input is provided for generating a program/verify read mode signal. The D-input is coupled to a V.sub.pp /OE control terminal of the EPROM, while the clock input is coupled to a CE/PGM control terminal. During a program interval, while an enabled memory cell is being programmed, and the V.sub.pp control terminal is at a supervoltage, the latch is operable to capture the high level on such control terminal, and provide the high level as an output to define a verify read mode signal. During an immediately-following program verify read interval, the asserted verify mode signal is used to adjust the sense amplifier of the EPROM device so as to provide an increased read margin. During such verify program interval, the V.sub.pp /OE control terminal goes low to enable the outputs of the EPROM device. Such low signal is captured by the latch during the verify interval using the CE/PGM signal as a clock, such that the verify mode signal is driven low. With the verify mode signal in a logic low state, subsequent read operations of the EPROM chip occur as standard reads, since the sense amplifiers associated with the memory array of the EPROM device employ a standard reference signal, not the verify reference signal designed to add read margin.

Test mode latching scheme

A memory circuit with a low power programming voltage switch for reduced leakage current during a read operation. The apparatus includes a high voltage switch which, in a programming mode receives a high (e.g. programming) voltage and in another mode (reading) receives a normal range voltage, and a line driver which drivers a selection or non-selection voltage into word lines or column select lines into a memory array. During a read mode, the deselected line drivers and high voltage switches are operated in a reduced leakage current mode such that leakage current is forced through selected line drivers and their high voltage switches before being forced through the deselected line drivers such that the leakage current is limited to the number of selected line drivers.

Low power high voltage switch with gate bias circuit to minimize power

A pseudo-differential sense amplifier for sensing the state of an array memory cell by reference to a reference cell in a predetermined state. The sense amplifier has an input stage coupled to the array memory cell, which provides signals to a differential stage from which an output is generated. The input stage has reference and array side cascode circuits in which the components are matched on each side so as to eliminate process, temperature, and other extraneous variations from influencing the differential output. An enabling signal to the array side of the input stage is delayed with respect to the reference side such that voltage fluctuations externally introduced into the signals passed from the input stage to the differential stage do not cause erroneous switching and/or glitches to appear at the sense amplifier output. Additionally, parallel cascode and load transistors can be selectively switched into the input stage circuit to enable selectable cascode transconductance and circuit loading to effect selectable speed and/or input stage voltage swing.

Pseudo-differential sense amplifier

A variable slew control for output circuits is disclosed. The slew control circuit automatically adjusts the rate in which voltage on a slew node is driven to a reference voltage, minimizing noise at the output device driver. The variable slew control decreases the slew rate of the slew node during periods when di/dt is at a high level, but allows the voltage on the slew node to drop at faster rates during times when di/dt at the output driver is low.

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Pleasanton, CA, United States of America

Sammy S Cheung