Marvell International Limited

Denali Software, Inc.

Samitinjoy Pal

Jun Zhu

Joseph Jun Cao

Steven Lee Shrader

Michael McKeon

Can Ma

Hongyan Liu

Art Gmurowski

Anne Espinoza

A system including a storage device and a controller. The storage device is configured to store a map. The map relates (i) a first portion of a memory to a first order of first dimensions, and (ii) a second portion of the memory to a second order of second dimensions. The first portion of the memory and the second portion of the memory are non-overlapping. Each of the first dimensions and each of the second dimensions has corresponding memory cells in the memory. The controller is configured to control access to the first portion of the memory according to the first order of first dimensions while controlling access to the second portion of the memory according to the second order of the second dimensions.

Apparatus and method for accessing non-overlapping portions of memory according to respective orders of dimensions

A system including a register and a controller. The register is configured to store a map relating distinct regions of a memory to respective mapping modes. Each of the mapping modes identifies a predetermined order of dimensions of a respective region of the memory. Each of the dimensions of the regions of the memory is identified as a row, a bank, or a column. The mapping modes include (i) a first mapping mode having a first predetermined order of dimensions, and (ii) a second mapping mode having a second predetermined order of dimensions that is different from the first predetermined order of dimensions associated with the first mapping mode. The controller is configured to control access to the distinct regions of the memory according to the map stored in the register, including controlling access to a first region of the memory according to the first mapping mode while controlling access to a second region of the memory according to the second mapping mode.

System and method for accessing distinct regions of memory using multiple mapping modes, each of the mapping modes having a predetermined order of dimensions for a respective region of the memory

A method of mapping system addresses to physical addresses associated with a physical memory device receives memory requirements associated with an application, allocates a region of the physical memory device to the application (wherein the region is a contiguous portion of the physical addresses that does not overlap with any other region and is associated with a memory mapping mode), determines a memory mapping scheme for the region (wherein the memory mapping scheme defines the mapping between system addresses and the region and is based at least on the memory mapping mode) and modifies a mapping register to reflect the region. In one implementation, the method modifies the mapping register to reflect the memory mapping scheme. In another implementation, the memory requirements comprise an application type, and the memory mapping mode is determined based on the application type.

System and method for mixed-mode SDRAM address mapping

A port independent data transaction interface for multi-port devices is provided. The port independent data transaction interface includes a command channel that receives command data and a source id. The source id indicates a source device that transmitted the command data. In addition, a data-in channel is included that receives write data and a write source id. Similar to the source id, the write source id indicates a source device that transmitted the write data. The port independent data transaction interface further includes a data-out channel that provides read data and a read id. The read id indicates a source device that transmitted a read command corresponding to the read data. The port independent data transaction interface utilizes the source id to associate command data with corresponding write data and read data.

Port independent data transaction interface for multi-port devices

An interface for sending write data, write control signals and write data between a memory controller and a double data rate (DDR) memory with the appropriate timing relationships so that the write data can be reliably written in the DDR memory. Also, an interface for reliably capturing read data received from the DDR memory during a read operation.

Input/output cells for a double data rate (DDR) memory controller

Circuitry for programming the amount of delay applied to an input signal, the circuitry performing the method of determining the number of delay elements required to capture a clock cycle, receiving a programmable delay value and calculating the number of delay elements required to delay a clock signal by the received delay value and delaying the clock signal by the number of delay elements required to delay the clock signal by the programmable delay value.

Growing community of inventors

Santa Cruz, CA, United States of America

Samitinjoy Pal