Emc IP Holding Company LLC

Micron Technology Incorporated

Samir Rajadnya

Michael Nishimoto

Karthik Ramachandran

Todd Wilde

Samir Mittal

Anirban Ray

Gurpreet Anand

Paul Roger Stonelake

Parag R Maharana

Richard Van Gaasbeck

Bruce Wong

A processing device, operatively coupled with one or more memory devices, is configured to provide a plurality of virtual memory controllers, partition one or more memory devices into a plurality of physical partitions, and associate each of the plurality of virtual memory controllers with one of the plurality of physical partitions. The processing device further provides a plurality of physical functions, wherein each of the plurality of physical functions corresponds to a different one of the plurality of virtual memory controllers, and presents the plurality of physical functions to a host computing system over a peripheral component interconnect express (PCIe) interface.

NVMe direct virtualization with configurable storage

A system controller, operatively coupled with one or more memory devices, is configured to provide a plurality of virtual memory controllers, wherein each of the plurality of virtual memory controllers is associated with a different portion of the one or more memory devices, and provide a plurality of physical functions, wherein each of the plurality of physical functions corresponds to a different one of the plurality of virtual memory controllers. The system controller further presents the plurality of physical functions to a host computing system over a peripheral component interconnect express (PCIe) interface, the host computing system to assign each of the plurality of physical functions to a different virtual machine running on the host computing system.

In general, embodiments of the technology relate to a method and system for storing and reading data from persistent storage. More specifically, embodiments of the technology relate to a method and system for storing data in persistent storage, where the data written to the persistent storage is not immediately accessible in the persistent storage (i.e., during the inaccessibility period). In such instances, embodiments of the technology provide a method and system to enable the storage system to service read requests for the data using a primary cache entry table (PCET) and an overflow table.

Method and system for writing data to and read data from persistent storage

In general, embodiments of the technology relate to a method and system for performing fast ordered writes in a storage appliance that includes multiple separate storage modules. More specifically, embodiments of the technology enable multicasting of data to multiple storage modules in a storage appliance, where the order in which the write requests are processed is the same across all storage modules in the storage appliance.

Method and system for fast ordered writes with target collaboration

Method and system for fast ordered writes with atomic multicast

One or more virtual functions are exposed via a shared communication interface. Memory across said virtual functions is shared to provide a fixed number of I/O buffers shared across said virtual functions. For each of said one or more virtual functions, storing a corresponding map table configured to store a mapping data that maps a logical block address of the virtual function to a corresponding allocated one of said fixed number of I/O buffers based at least in part on a current state of a state machine.

Virtual I/O queuing

One or more virtual functions is exposed via a shared communication interface. A plurality of I/O buffers shared across said virtual functions are provided. For each of said one or more virtual functions, a corresponding submission queue comprising one or more virtual submission queue entries (SQEs) is used, wherein a memory access device is configured to: receive data pushed to the memory access device by a client host system, store the data in an allocated one of the I/O buffers, receive a submission queue entry (SQE) that invokes one of said virtual functions with respect to the data, and use a corresponding one of the plurality of logic circuits that is associated with the invoked virtual function to perform the virtual function with respect to the data as stored in the allocated I/O buffer.

Host to device I/O flow

A request is received via a message submission queue. The request is sent from a core associated with an external processor coupled by a communication interface. The message submission queue is associated with a memory access engine circuit configured to perform one or more memory access functions. The memory access engine circuit is used to dequeuer a next message from its corresponding message submission queue. The memory access engine circuit is used to perform a message function invoked by the message. The memory access engine circuit is used to receive a result of performing the message function. The memory access engine circuit is used to prepare and send to an external processing core that sent the message a response message determined based at least in part on the result.

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San Jose, CA, United States of America

Samir Rajadnya