International Business Machines Corporation

Other

Samir Kirit Patel

Frank David Ferraiolo

Joseph M Hoke

William Vincent Huott

Gary A Van Huben

Kevin M McIvain

Chin-Long Chen

Vincenzo Condorelli

Edward W Chencinski

Leonard L Fogell

A method for fabricating a circuit comprises identifying a target on the circuit with a transitional sensitivity, determining a test pattern that stresses the target, generating a verification model at the hierarchy of the target, creating a pattern and translating the pattern into a verification assertion, running the verification with the translated pattern, determining whether the verification assertion is a possible verification assertion following the running of the verification, obtaining a state of source laches and pin inputs responsive to determining that the formal verification assertion is a possible verification assertion following the running of the formal verification, translating the formal verification assertion into a coverage event, running a simulation with the coverage event, determining whether the coverage event occurred, and creating a manufacturing test responsive to determining that the coverage event occurred.

Physically aware test patterns in semiconductor fabrication

A method for fabricating a circuit comprises identifying a target on the circuit with a transitional sensitivity, determining a test pattern that stresses the target, generating a verification model at the hierarchy of the target, creating a pattern and translating the pattern into a verification assertion, running the verification with the translated pattern, determining whether the verification assertion is a possible verification assertion following the running of the verification, obtaining a state of source latches and pin inputs responsive to determining that the formal verification assertion is a possible verification assertion following the running of the formal verification, translating the formal verification assertion into a coverage event, running a simulation with the coverage event, determining whether the coverage event occurred, and creating a manufacturing test responsive to determining that the coverage event occurred.

The modular exponentiation function used in public key encryption and decryption systems is implemented in a standalone engine having at its core modular multiplication circuits which operate in two phases which share overlapping hardware structures. The partitioning of large arrays in the hardware structure, for multiplication and addition, into smaller structures results in a multiplier design comprising a series of nearly identical processing elements linked together in a chained fashion. As a result of the two-phase operation and the chaining together of partitioned processing elements, the overall structure is operable in a pipelined fashion to improve throughput and speed. The chained processing elements are constructed so as to provide a partitionable chain with separate parts for processing factors of the modulus. In this mode, the system is particularly useful for exploiting characteristics of the Chinese Remainder Theorem to perform rapid exponentiation operations. A checksum mechanism is also provided to insure accurate operation without impacting speed and without significantly increasing complexity. While the present disclosure is directed to a complex system which includes a number of features, the present application is particularly directed to circuits and methods for carrying out modular exponentiation.

Circuits and methods for modular exponentiation

A tonal adjusting device for selectively changing the pitch of one or more strings of a guitar. The tonal adjusting device includes a lever assembly with upper and lower arms that are designed for being positioned around the neck of a stringed instrument. The upper arm has dampening members for selectively engaging the strings when the upper arm engages the face of the neck of the instrument.

Tonal adjusting device

Frequency differences between differing clock sources are compensated for by an adaptive filtering mechanism. An amount of frequency drift between two clock sources is determined. Then, based on that amount of frequency drift, a filtering value is selected to be used in tracking the frequency drift. If the frequency drift is determined to be large, then a minimum filtering value is selected. However, if it is determined to be small, then a maximum filtering value is selected. The selected filtering value is used to adjust the address(es) of one or more data bits being transmitted and received using the two clock sources, such that the frequency drift is properly tracked.

Adaptive filtering method and apparatus to compensate for a frequency

A serial data stream is recovered using a local clock, which is asynchronous to the clock used to transmit the serial data. The incoming serial data stream is phase shifted or delayed by a digital phase-locked loop so that it may be reliably sampled by the local clock. The DPLL samples the serial data stream and captures data on both the rising and falling edges of the local clock employing three edge detectors. This partitions the data stream into two bit samples, which the DPLL presents to a deserializer. The deserializer converts the serial data to parallel data and assembles the received data back into data bytes. The deserializer also generates a received byte clock used for presenting the parallel data to, for example, the ESCON channel logic.

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Wappingers Falls, NY, United States of America

Samir Kirit Patel