Avago Technologies General IP (singapore) Pte. Ltd.

Avago Technologies International Sales Pte. Limited

Avago Technologies General IP Pte, Ltd.

Avago Technologies Fiber IP (singapore) Pte. Ltd

Samir Aboulhouda

Faouzi Chaahoub

Georgios Asmanis

Fesseha Tessera Seifu

Marco Fornasari

Michael Allen Robinson

Sriramkumar Sundararaman

Ajay Kumar Yadav

Ramana Murty Malladi

Ronald T Kaneshiro

Chakravartula Nallani

Kartikeya Gupta

Ravi Teja Kotamraju

Ahmed Rashid Syed

David George Cunningham

Kazi Asaduzzaman

A CDR circuit for use in an optical receiver is provided that performs automatic rate negotiation. The CDR circuit is configured to determine whether the incoming data signal has a first, second or third data rate. If the CDR circuit determines that the incoming data signal has the first data rate, the CDR circuit places itself in a bypass mode of operations so that CDR is not performed. If the CDR circuit determines that the incoming data signal has the second or third data rates, the CDR circuit places itself in a CDR mode of operations and performs CDR on the incoming data signal.

Clock-and-data recovery (CDR) circuitry for performing automatic rate negotiation

A control device that may be implemented in a single IC chip is provided that is capable of controlling EAM bias voltages and DFB bias currents and of monitoring the EAM photocurrents and received signal strength indicators (RSSIs) in a multi-channel optical transceiver module. The control device IC chip can be manufactured at relatively low cost with relatively high yield, and can be implemented in a relatively small area. To implement the control device in a single IC chip, multiple supply voltage domains are used in the IC chip, one of which is a negative supply voltage domain and one of which is a positive supply voltage domain. In order to provide these different supply voltage domains, a level shift circuit is employed in the IC chip that converts signals from the positive to the negative supply voltage domain, and vice versa, and changes the voltage levels, as needed.

Control device and method for controlling biasing of multiple light sources of multiple channels of a multi-channel optical communications module

A low power data retiming circuit incorporates CMOS components in certain sections that operate at a lower frequency in comparison to certain other sections that use components based on bipolar technology for operating at a relatively higher frequency. The data retiming circuit includes a clock recovery circuit wherein a voltage controlled oscillator provides a recovered clock to a clock generator circuit for generating a latched clock that is provided to a phase detector and a data serializer. The data serializer operates as a synchronous multiplexer for generating a retimed data output signal from a pair of latched data input signals. The phase detector and the data serializer operate in a half-rate mode wherein high and low voltage levels of the latched clock are used for clocking data. The half-rate mode of operation permits the use of a clock frequency that is half that of an input data rate.

Integrated circuit incorporating a low power data retiming circuit

An equalizer that includes equalizer circuitry, a mean squared error (MSE) system, and adaptive control logic includes features that inhibit undesirable convergence to local minima.

Adaptive equalizer

An optical communications system and method at least doubles the data rate of the optical fiber link without requiring a redesign of the backplane ASIC. This is made possible in part through the incorporation of at least one gearbox integrated circuit (IC) is incorporated into the system that is compatible with the current ASIC design. The gearbox IC receives N lanes of electrical data signals from the ASIC, with each electrical data signal having a data rate of X Gbps, and outputs N/2 lanes of electrical data signals, with each electrical data signal having a data rate of 2X Gbps. The high-speed optical transceiver module receives the N/2 electrical data signals output from the gearbox IC and produces N/2 respective optical data signals having a data rate of 2X Gbps for transmission over the optical fiber link.

High-speed optical fiber link and a method for communicating optical data signals

A rate-adaptive equalizer automatically initializes its tap coefficients to values. During an initialization process, a linear search algorithm is performed that sweeps the tap coefficients through different combinations of tap coefficients while assessing information about an eye associated with an input signal received over a communications channel. When the eye information indicates that the eye is open, the current tap coefficients are selected as the initial tap coefficients to be used at the beginning of the main adaptation algorithm.

Rate-adaptive equalizer that automatically initializes itself based on detected channel conditions, and a method

A gearbox IC is incorporated into an optical communications system to enable an optical link that incorporates the system to achieve data rates that are at least double that which are currently achievable in optical links. The gearbox IC performs data rate conversion and phase alignment. In the transmit direction, the gearbox IC receives N lanes of electrical data signals having a data rate of X Gbps and outputs N/2 lanes of electrical data signals having a data rate of 2X Gbps. In the receive direction, the gearbox IC receives N/2 electrical data signals having a data rate of 2X Gbps and converts the N/2 electrical data signals into N electrical data signals having a data rate of X.

Method and apparatus for performing data rate conversion and phase alignment

A fiber optic link is provided that uses a relatively low-cost transceiver that incorporates relatively inexpensive low bandwidth optical and electrical components to achieve high data rate operations. The data rate of the fiber optic link can be greater than the data rate of the laser of the transceiver provided the laser meets certain noise requirements; in particular, the relative intensity noise (RIN) of the laser must be low enough to ensure low bit error rate (BER) operation of the link.

Fiber optic link, a transceiver for use in the link, and methods for designing and constructing fiber optic links and transceivers

An averaging circuit apparatus comprises a rectifier having an input for receiving a high-speed error signal having, for example, a data rate of 10 Gbps. An integrator is coupled to the rectifier and has an error output for providing an averaged representation of the error signal. The averaged representation of the error signal is supplied to a Digital Signal Processor in a channel equalizer loop for equalizing a fiber-optic channel. The Digital Signal Processor executes an algorithm that sets tap coefficients of an analogue filter in response to the averaged representation of the error signal.

Averaging circuit apparatus, error signal generation system and method of averaging an error signal

An integrated circuit comprises a gain stage circuit coupled to a compensation circuit. Both the gain stage circuit and the compensation circuit respectively comprise a first current source and a second current source that are subject to the same process variations. A negative feedback circuit is used to generate a corrective current in relation to the second current source, indicative of a current that needs to flow through a load in addition to a current flowing through the second current source in order for a variable voltage to be substantially equal to a reference voltage used to drive the first and second current sources. A compensating current corresponding to the corrective current generated for the second current source is applied to the first current source to compensate for process variation in the gain stage circuit in respect to the first current source.

Integrated circuit apparatus and method of compensating a current

A variable gain feedback amplifier circuit comprising a degenerated common emitter circuit coupled to an emitter follower circuit, an output of the emitter follower circuit being coupled to an input of the degenerated common emitter circuit via a variable feedback impedance. An automatic gain controller is coupled to the variable feedback impedance in order to reduce a closed loop gain of the variable gain feedback amplifier circuit when required. The degenerated common emitter circuit also comprises a variable emitter impedance that is also controlled by the automatic gain controller so as to counteract a lowering effect of a reduction in the variable feedback impedance on the open-loop gain of the variable gain feedback amplifier circuit.

Variable gain feedback amplifier circuit apparatus and method therefor

A Root Mean Square (RMS) detector circuit includes a first differential pair circuit arranged to operate in a common mode. The detector circuit also includes a compensation circuit unit having a second differential pair circuit to duplicate an unwanted base current drawn by the first differential pair circuit. The compensation circuit unit is arranged to generate an offset voltage using the duplicated base current. The compensation circuit unit also has an operational amplifier coupled to an NMOS transistor so as to generate a corrective current corresponding to the offset voltage, the corrective current being mirrored by a current mirror and provided as a compensatory current to an input of the first differential pair circuit.

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Cupertino, CA, United States of America

Samir Aboulhouda