Stmicroelectronics International N.v.

Stmicroelectronics Application Gmbh

Samiksha Agarwal

Vivek Mohan Sharma

Nicolas Bernard Grossier

Deepak Baranwal

Roberto Colombo

In an embodiment a processing system includes a test circuit configured to set an address value, an upper address limit and a lower address limit to a given reference bit sequence, verify whether the upper-limit comparison signal has a respective third logic level and/or whether the lower-limit comparison signal has the respective third logic level, assert an error signal in response to determining that the upper-limit comparison signal does not have the respective third logic level or the lower-limit comparison signal does not have the respective third logic level, repeat a certain operation for each of the N bits.

Processing system, related integrated circuit, device and method

In an embodiment, a method includes: receiving, with a first buffer of a first error compactor unit (ECU), a first error packet associated with a first circuit; receiving, with the first buffer, a second error packet associated with a second circuit; transmitting a first reading request for reading the first error packet; receiving the first reading request with an arbiter of an error aggregator unit (EAU) of a central error management circuit; in response to receiving the first reading request, reading the first error packet from the first buffer, transmitting the first error packet to a controller of the central error management circuit, and transmitting a first acknowledgement to the first ECU; receiving the first acknowledgement with the first ECU; and in response to receiving the first acknowledgement, transmitting a second reading request for reading the second error packet.

Circuit and method for capturing and transporting data errors

In an embodiment, a method includes: receiving, with a first buffer of a first error compactor unit (ECU), a first memory error packet associated with a first memory; receiving, with the first buffer, a second memory error packet associated with a second memory; transmitting a first reading request for reading the first memory error packet; receiving the first reading request with an arbiter of an error aggregator unit (EAU) of a central memory error management unit (MEMU); in response to receiving the first reading request, reading the first memory error packet from the first buffer, transmitting the first memory error packet to a controller of the central MEMU, and transmitting a first acknowledgement to the first ECU; receiving the first acknowledgement with the first ECU; and in response to receiving the first acknowledgement, transmitting a second reading request for reading the second memory error packet.

A data synchronization unit including first flip-flops, operating on a first clock domain and a reset of a second clock domain, sampling data from the first clock domain; a second flip-flop, operating in the first clock domain, sampling a request signal when enabled by a request pulse; a request signal path configured to delay the request signal by a first delay and to generate an enable signal for recirculation multiplexers in accordance with the delayed request signal; a reset signal synchronization path configured to delay the reset signal of the first clock domain by a second delay, wherein the second delay is shorter than the first delay; and multiplexers having first inputs for receiving outputs of the recirculation multiplexers, a second input for receiving a reset value of a programmable register, the multiplexers being configured to selectively output signals at inputs to outputs.

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New Delhi, India

Samiksha Agarwal