Intel Corporation

Samie B Samaan

Stephan Jourdan

Fabrice Paillet

David W Grawrock

Gerhard Schrom

Edward Allyn Burton

Shahrokh Shahidzadeh

Sergiu D Ghetie

Jonathan P Douglas

Paul D Madland

Bruce Querbach

Tieyu Zheng

Alexander Lyakhov

Keshavan K Tiruvallur

Mark B Trobough

Chinna B Prudvi

Neeraj S Upasani

Hermann Gartler

Vui Yong Liew

William Dawson Kesling

George L Geannopoulos

Gary Leonard Woods

Ashok N Kabadi

Keith A Drescher

Daniel G Borkowski

J Keith Hodgson

Mukesh Kataria

Narayanan Natarajan

Jay Joseph Nejedlo

Victor Zia

Lyle E Cool

Michael J Tripp

Narayanan Raghuraman

Russell J Wunderlich

James J Grealish

Brian Meyer

Abhijit Davare

Chiu Keung Tang

Priyadarsan Patra

Ridvan A Sahan

William Penner

Ravi Sankar Vunnam

Rahima K Mohammed

Wee Hoo Cheah

Vijaya K Boddu

Arun R Ramadorai

Marijan Persun

Kapila B Udawatta

Yuen Tat Lee

John L Baudrexl

Christian E Iovin

Won Lee

Loren James McConnell

Michael W Rogers

Kyle Markley

Kip C Killpack

Padmakumar Gopal

Neil Dobler

Nagib Z Hakim

Timothy S Storey

Yi Amy Xia

Edwin E Parks

Robert M Spencer

Andrew E Allen

Sanjay S Salem

Travis K Goff

Evan J Halprin

David C Florey

Selvakumar Raja Gopal

Jiun Long Foo

Kenneth Young

An apparatus and method is described herein for providing a test, validation, and debug architecture. At a target or base level, hardware hooks (Design for Test or DFx) are designed into and integrated with silicon parts. A controller may provide abstracted access to such hooks, such as through an abstraction layer that abstracts low level details of the hardware DFx. In addition, the abstraction layer through an interface, such as APIs, provides services, routines, and data structures to higher-level software/presentation layers, which are able to collect test data for validation and debug of a unit/platform under test. Moreover, the architecture potentially provides tiered (multiple levels of) secure access to the test architecture. Additionally, physical access to the test architecture for a platform may be simplified through use of a unified, bi-directional test access port, while also potentially allowing remote access to perform remote test and debug of a part/platform under test. In essence, a complete test architecture stack is described herein for test, validation, and debug of electronic parts, devices, and platforms.

Test, validation, and debug architecture

In one embodiment, a processor includes: a first die including at least one processor core to execute instructions and a non-volatile storage to store an identifier to be provisioned into the processor during manufacture; a second die to couple to the first die, the second die including a wireless circuit and a second non-volatile storage; and a wireless interface to couple to the second die to enable wireless communication with a wireless device. The processor may be disabled if the identifier is not stored in the second non-volatile storage. Other embodiments are described and claimed.

System, apparatus and method for securely protecting a processor in transit

Described is an apparatus having a non-linear control to manage power supply droop at an output of a voltage regulator. The apparatus comprises: a first inductor for coupling to a load; a capacitor, coupled to the first inductor, and for coupling to the load; a first high-side switch couple to the first inductor; a first low-side switch coupled to the first inductor; a bridge controller to control when to turn on and off the first high-side and first low-side switches; and a non-linear control (NLC) unit to monitor output voltage on the load, and to cause the bridge controller to turn on the first high-side switch and turn off the first low-side switch when a voltage droop is detected on the load.

Non-linear control for voltage regulator

Embodiments of the present invention relate to a system and method for implementing functions of a register translation table of a computer processor, with reduced area requirements as compared to known arrangements. In one embodiment, an apparatus may comprise a register alias table cache to map a logical register to a physical register. The register alias table cache may have a capacity corresponding to a subset of architectural logical registers. The apparatus may further comprise store logic coupled to the cache to perform operations to save an existing content of the physical register if a cache entry corresponding to the logical register is evicted from the cache. The apparatus may also comprise load logic coupled to the cache to perform operations to load a content to the physical register and to form a new entry in the cache if a needed mapping is not present in the cache.

Register alias table cache to map a logical register to a physical register

A method, apparatus, article of manufacture, and system, the method including, in some embodiments, performing an in-system (or in-the-field) self-test on a first core of a multi-core (or multi-CPU) processor to obtain at a value for at least one operational parameter of the first core, storing the value for the at least one operational parameter of the first core, testing, under control of the first core, at least one of a remaining set of cores of the multi-core processor to determine a value for the at least one operational parameter for the at least one core of the remaining set of cores, and testing, under control of the at least one core of the remaining set of cores, the first core to determine a value for the at least one operational parameter for the first core.

Method and system to self-test single and multi-core CPU systems

A system may include M cache entries, each of the M cache entries to transmit a signal indicating a read from or a write to the cache entry and comprising a data register and a memory address register, and K layers of decision cells, where K=logM. The K layers M/2 decision cells of a first layer to indicate the other one of the respective two of the M cache entries and to transmit a hit signal in response to the signal, a second layer of M/4 decision cells to enable the other one of the respective two of the M/2 decision cells of the first layer and transmit a second hit signal in response to the signal, a (K&#x2212;1)th layer of two decision cells to enable the other one of the respective two decision cells of the (K&#x2212;2)th layer and transmit a third hit signal in response to the second hit signal, and a Kth layer of a root decision cell to enable the other one of the respective two decision cells of the (K&#x2212;1)th layer in response to the third hit signal.

Determination of cache entry for future operation

A leakage inverter has a switching delay in one direction that is directly proportional to the drain or gate leakage current of either an n-type or p-type device. For one aspect, a leakage ring oscillator includes an odd number of inverters including at least one leakage inverter such that the frequency of oscillation of the leakage ring oscillator is directly proportional to local device leakage. For another aspect, a leakage ring oscillator may be used to indicate temperature and/or temperature variation on a die.

Method and apparatus for measuring relative, within-die leakage current and/or providing a temperature variation profile using a leakage inverter and ring oscillator

An array of circuitry forming row and column ring oscillators is provided to determine aberrant gates in an integrated circuit. Control logic is coupled to the rows and columns to enable a ring oscillator of either a row or a column to oscillate. Based on outputs of these oscillations, aberrant gates in an integrated circuit may be more readily studied.

Ring oscillator gates in a matrix for aberrant logic gate timing detection

A device and method for probing high-speed local supply voltage fluctuations in VLSI circuits. The device includes a voltage probe coupled to a source of the local supply voltage, the voltage probe detectably emitting infrared radiation having an intensity that is related to a magnitude of the local supply voltage. The method includes emitting infrared radiation having an intensity that is related to the magnitude of the local supply voltage, taking initial measurements of the emitted radiation intensity for a range of supply voltages while digital activity is suspended in a vicinity of the local voltage probe, and compiling a calibration table matching measured intensity values with a magnitude of the supply voltage. Thereafter, digital activity is initiated by running a repetitive pattern through circuitry in the vicinity of the local voltage probe, where the repetitive pattern stimulates local supply voltage fluctuation events. Samples of emitted radiation intensity are taken using a time correlated photon counting or equivalent time sampling process and local supply voltage fluctuations are determined from the detected radiation.

Device and method for probing instantaneous high-speed local supply voltage fluctuation in VLSI integrated circuits using IR emissions

A high-speed, state-preserving, race-reducing, wide-pulsed clock domino design style. For one aspect, a pipestage in accordance with the wide-pulsed clock design style includes one or more domino logic stages and a wide-pulsed clock generator to provide a wide-pulsed clock signal to control evaluation of the one or more domino logic stages in response to receiving a two-phase input clock signal. The wide-pulsed clock signal has a pulse width that tracks a phase width of the input clock signal over a first frequency range where the first frequency range extends at least from a predetermined fraction of a nominal clock frequency to an upper frequency limit for the circuit. For one aspect, ratio logic is coupled to at least one of the domino stages. The wide-pulsed clock signal provides sufficient time for the one or more domino logic stages to evaluate while preventing infinite or very long contention in one or more ratio logic stages when the input clock signal is stopped or slowed down significantly.

High-speed, state-preserving, race-reducing, wide-pulsed-clock domino design style

A technique for probing parameter variations in an integrated circuit chip includes providing a group of ring oscillators disposed over the integrated circuit chip, each oscillator producing an output representative of an integrated circuit chip parameter or group of parameter. A controller is provided to selectively enable one of the group of ring oscillators and a multiplexer is provided to output an output of one of the group of ring oscillators enabled by the controller. Each ring oscillator may include a gated inverter, having an enable/disable input, connected to a group of inverters arranged in a ring, the total number of inverters being an odd number. The group of ring oscillators may include a shift register chain consisting of a group of shift registers, an output of each shift register being respectively connected to an enable/disable input of the gated inverter of one of the group of ring oscillators. The multiplexer may include an exclusive-OR gate having inputs respectively connected to an output of each of the group of ring oscillators. An inverter may be disposed between each output of the group of ring oscillators and its' respective input to the multiplexer.

Parameter variation probing technique

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Lake Oswego, OR, United States of America

Samie B Samaan