Nvidia Corporation

Sami Olavi Johannes Kiminki

Wishwesh Anil Gandhi

Mark Hairgrove

Liang Yin

Karan Mehra

Sujoyita Kaushikkar

Alexander Michael Waterman

Jeff Smith

Daniel Glenn Robinson

Anup Holey

A processing device including a first cache is coupled to a system memory and a parallel processing unit (PPU) including a second cache. An operation to modify cache lines of the second cache associated with a first aperture of the system memory is received. A first subset of cache lines of the second cache is identified. The first subset of cache lines is associated with the first aperture of the system memory and is different from a second subset of cache lines of a second aperture of the system memory. The first subset of cache lines is modified as specified by the cache operation.

Systems and methods for aperture-specific cache operations

Growing community of inventors

Espoo, Finland

Sami Olavi Johannes Kiminki