Texas Instruments Corporation

Sami Kiriaki

William Robert Krenik

Shivaling S Mahant-Shetti

Indumini W Ranmuthu

Krishnasawamy Nagaraj

Davy H Choi

Kerry C Glover

Khen-Sang Tan

Kenneth M Bell

Mark A Wolfe

Yong Han

Bogdan Staszewski

A novel Finite Impulse Response ('FIR') filter () is provided with. A master/slave sample and hold architecture is employed. In this architecture, an input signal (V) is coupled to an input of a master sample and hold circuit (). At least two slave sample and hold circuits () connect to the master output. The slave sample and hold circuits () operate at 1/k times the clock rate of the master sample and hold circuit (), where k equals the number of slave sample and hold circuits (). A first multiplexer () multiplexes the slave outputs together. At least one tap block () is coupled to the first multiplexer () includes a multiplier (), a summer (), at least two slave sample and hold circuits () and a second multiplexer (). The slave sample and hold circuits () run at 1/k times the clock speed of the master sample and hold circuit ().

Transpose FIR filter architecture

Preamplifiers are used in hard disk drive applications to read data stored on magnetic disk. Current bias current sense preamplifiers have a problem with bandwidth rolloff due to relatively high inductance. Voltage sense preamplifiers have a problem with peaking due to input capacitance. An improved current bias voltage sense preamplifier inserts a PMOS transistor M between the Rmr head and the bipolar transistor Q . The PMOS transistor M and the bipolar transistor Q form a high impedance voltage sense preamplifier. Biasing of the MR head is performed transistors M and M that mirror the current supplied by the current digital to analog converter into the MR head. Hence, the preamplifier is also of the current bias type. Peaking is controlled through a programmable current in an input capacitance cancellation circuit

Current bias voltage sense single ended preamplifier

High-bandwidth, analog multiplexer circuits with low signal feed-through and good common mode properties are described. These are BiCMOS circuits with N-MOS control transistors which emphasize low parasitic capacitance through circuit layout techniques and the use of smaller geometry devices where possible. These circuits can be used in both single-ended and differential configurations and address applications having multiplexing ratio requirements ranging from 2-to-1 up to many-to-1.

Analog BiCMOS multiplexers with CMOS control signals

A monolithic, low power, digital-to-analog converter (DAC) circuit which uses an efficient transistor element to perform both switching and resistive current division functions simultaneously. This allows a R-2R type ladder network to be built using only conventional MOS transistors which can both switch and accurately divide current among the branches of the ladder network, without the need for separate resistors. The lower parts count and requirement for MOS transistors only, without the need for separate resistors, makes this circuit very compatible with low cost monolithic implementation. The DAC of this patent is useful in an application requiring the multiplication of two analog signals, where one of the signals is presented as a digital word. In this application, a Gilbert multiplier circuit is used to multiply the two signals, V and V , where V represents the binary-weighted discrete levels from the DAC and V is a continuous analog signal. Additionally, in order to obtain linear multiplication over a wide range, the Gilbert multiplier requires the use of a predistortion circuit in conjunction with the V signal coming from the DAC to compensate for the logarithmic current-voltage transfer function of this circuit.

MOS transistor digital-to-analog converter

The invention comprises a differential sample-and-hold circuit including a differential gain stage. The differential gain stage comprises a control transistor and an output node. The differential gain stage further comprises a primary load coupled between the control transistor and the output node. A hold control circuit is coupled to the base of the control transistor, the hold control circuit operable to effect a reduction of the base voltage of the control transistor and a corresponding reduction of the voltage at the output node of the differential gain stage.

Sample-and-hold circuit

The invention relates to the interfacing of high speed, low voltage data streams with CMOS circuits and, more specifically, to converting low voltage, differential ECL signals levels to higher voltage levels which are compatible with CMOS circuits while maintaining high speed and sufficient drive capability. This is accomplished by making first stage inverters,and,as geometrically small as possible subject to the design rules in use to minimize the capacitance at the input of these inverters. The inputs of the first stage inverters are clamped by bias circuits,and,at DC levels so as to provide a narrow range of operation. Additional output inverters,and,act as buffers to provide the needed capacitive load drive capability.

Differential, high speed, ECL to CMOS converter

A read channel circuit includes a digital partition and a analog portion coupled by an ADC. This digital portion and the analog portion are on different chips and the analog portion is positioned on the flex.

HDD chip set partitioning

This invention relates to interfacing high speed, low voltage, data streams with CMOS circuits and, more specifically, to converting low voltage, differential, ECL signal levels to higher voltage levels which are compatible with CMOS circuits while maintaining high speed and sufficient drive capability for larger system applications. This is accomplished primarily by making the first stage inverters 5 and 6 as geometrically small as possible and providing additional cross-coupled buffers 7 and 8 capable of driving large capacitive loads.

A novel Finite Impulse Response filter (FIR) Filter is provided which includes a plurality of multipliers (14-22), a plurality of multiplexers (24-32), and a plurality of sample and hold circuits (34-42). At least two of the sample and hold circuit output signals (1-5) may be multiplexed in a round robin fashion to at least two of the multipliers (14-22). The multipliers may receive as a second input, fixed tap coefficient signals (C.sub.1 -C.sub.5) for multiplication with the multiplexed sample and hold circuit output signals (1-5).

Fir filter architecture

A novel Finite Impulse Response ('FIR') filter (10)' is provided with precise timing acquisition. A master/slave sample and hold architecture is employed. In this architecture, an input signal (VIN) is coupled to an input of a master sample and hold circuit (34). A plurality of slave sample and hold circuits (36-44) are coupled to the output of the master sample and hold circuit. The outputs of the slave sample and hold circuits (36-44) are multiplexed to a plurality of multipliers (14-22) in a round robin manner.

Fir filter architecture with precise timing acquisition

A sync detect circuit is comprised of two serial data registers (40) and (42), each for storing a single word. A plurality of current sources in current source banks (44) and (46) are operable to convert the bits in the stored sync word to a differential current domain. Depending upon the logic state, the currents are added on two lines (50) and (52). When the differential current falls below a predetermined limit, a frame sync signal is generated to latch the next and following words into a data latch (34). These are then transferred out to a system upon the generation of a system data clock.

Sync detect circuit

A metal-oxide-semiconductor digital-to-analog converter unit includes a multiplicity of current mirror components 20 in a symmetric array, a resistance network activated by voltage sources providing weighted biasing potentials for the current mirror components, and an electrical coupling of the current mirror components to compensate for variations physical properties across converter unit substrate area. The current mirror components 20 include a current steering portion 21.sub.0 -21.sub.N-1 and 25.sub.0 -25.sub.N-1 coupled to an annular bias transistor 22. The resulting digital-to-analog converter has improved performance characteristics when compared to previously implemented digital-to-analog converter units.

Apparatus and method for current steering digital-to-analog converter

An oversampled modulator (FIGS. 1 and 4) for operation in a frequency band from DC to a finyite frequency having a transfer function containing a plurality of zeros, at least two of which are disposed in the frequency band at a location other than at DC. The transfer function can have a plurality of zeros in the frequency band at a location other than at DC and at the same frequency. The second order version of the oversampled modulator has the transfer function: ##EQU1## where

Second order and cascaded 2-1 oversampled modulators with improved

A decode circuit which permits large address decoding (corresponding to an increase in the number of ROM words) and/or an increase in the number of bits per word line while preserving ROM speed. This is accomplished by providing a positive feedback arrangement at the decode circuit output to speed up the increase in voltage at the decode circuit output during the pulldown phase of the clock cycle. As the voltage at an output line of the decode circuit is increasing through a first p-channel transistor coupled to a voltage supply, a second n-channel transistor having its gate coupled to the decode circuit output line is turned on and thereby applies a ground potential to the gate of the first transistor. This ground potential causes the first transistor to conduct even more rapidly and thereby increase the voltage at the decode circuit output more rapidly. This, in turn, causes the second transistor to apply ground potential to the gate of the first transistor even more rapidly. The result is that the output of the decode circuit is raised to approximately the supply voltage during the pulldown portion of the clock cycle much more rapidly than in prior art decode circuits that do not use the positive feedback arrangement of the present invention. The result is that prior art circuits can be made to operate with greater speed or can be provided with additional word lines and/or bit lines without decrease in speed.

High speed ROM decode circuit

An analog to digital converter system (10) is disclosed which comprises an SAR logic circuit (12) which controls capacitor array control switches (14) which themselves control a capacitor array (16). A top plate (18) of the capacitor array (18) is selectively coupled to a coarse comparator (24) and a fine comparator (26). The outputs of the coarse comparator (24) and the fine comparator (26) are input into an error correction circuit (28). In operation, the coarse comparator (24) is used to approximate a predetermined number of the most significant bits of the digital word to be output by the system (10) while the fine comparator (26) is used to approximate the remaining bits of the digital word. In this manner, the coarse comparator (24) alone is subjected to the high voltages which might cause errors as a results of the hysteresis effect in the threshold voltages of the MOSFETs used to construct the comparators. The voltage shift as a result of this hysteresis is not a significant factor for the bits generated by the coarse comparator and as such the system (10) may accomplish high resolution analog to digital conversions.

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Garland, TX, United States of America

Sami Kiriaki