Broadcom Corporation

Texas Instruments Corporation

Broadcom Corpotation

Sami Issa

Gil I Winograd

Cyrus Afghahi

Esin Terzioglu

Ali Anvar

Baher S Haroun

Morteza Cyrus Afghahi

David Barry Scott

Uming U Ko

Shakti Shankar Rath

Morteza (Cyrus) Afghahi

Zeynep M Toros

A compact dynamic random access memory (DRAM) cell and highly efficient methods for using the DRAM cell are disclosed. The DRAM cell provides reading, writing, and storage of a data bit on an ASIC chip. The DRAM cell includes a first transistor acting as a pass gate and having a first source node, a first gate node, and a first drain node. The DRAM cell also includes a second transistor acting as a storage device and having a second drain node that is electrically connected to the first drain node to form a storage node. The second transistor also includes a second source node and a second gate node. The second source node is electrically floating, thus increasing the effective storage capacitance of the storage node.

Compact and highly efficient DRAM cell

An electronic system (). The system comprises circuitry (P) for receiving a system voltage from a voltage supply. The system also comprises circuitry (), responsive to the system voltage, for providing data processing functionality. The circuitry for providing data processing functionality comprises a critical path (CP) and the critical path comprises a plurality of transistors. At least some transistors in the plurality of transistors have a corresponding predetermined voltage operating limit corresponding to a predicted lifespan. The system also comprises circuitry () for indicating a potential capability of operational speed of the critical path. The system also comprises circuitry (CB) for coupling the system voltage to the critical path. Lastly, the system also comprises circuitry () for adjusting the system voltage, as provided by the voltage supply, in response to the circuitry for indicating a potential capability. In selected instances, the circuitry for adjusting adjusts the voltage supplied by the voltage supply to be a voltage greater than the predetermined voltage operating limit while still complying with the predicted lifespan.

Integrated circuit with dynamically controlled voltage supply

A single integrated circuit (). The integrated circuit comprises a first circuit () having a data path, the first circuit consisting of a first number of logic gates for performing a plurality of logic functions. The integrated circuit also comprises a circuit () for indicating a potential speed capability of the data path. The circuit for indicating comprises a second number of logic gates () for performing the plurality of logic functions, wherein the second number is less than the first number. The circuit for indicating also comprises additional circuitry () for representing parasitic characteristics in the data path.

Integrated circuit dynamic parameter management in response to dynamic energy evaluation

A power management system () in an electronic device (). The system comprises circuitry (), responsive to at least one system parameter, for providing data processing functionality, where the circuitry for providing data processing functionality comprises a data path (CP). The system alternatively or cumulatively also comprises circuitry () for indicating a potential capability of operational speed of the data path and/or circuitry () for indicating an amount of current leakage of the circuitry for providing data processing functionality. The system also comprises circuitry () for adjusting the at least one system parameter in response to either or both of the circuitry for indicating a potential capability and the circuitry for indicating an amount of current leakage.

The present invention relates to a synchronous self timed memory device. The device includes a plurality of memory cells forming a cell array, at least one local decoder interfacing with the cell array, at least one local sense amplifier and at least one local controller. The local sense amplifier interfaces with at least the decoder and cell array, and is adapted to precharge and equalize at least one line coupled thereto. The local controller interfaces with and coordinates the activities of at least the local decoder and sense amplifier.

Synchronous controlled, self-timed local SRAM block

A computer programmed to specify a design of a circuit for indicating a potential speed capability of a data path in a predetermined circuit. The data path comprises a plurality of logic functions to be performed by a first number of logic gates. The computer specifies the design by steps. In one step, the program specifies a second number of logic gates to be included in the circuit for indicating a potential speed capability. The second number of logic gates is less than the first number of logic gates and provides voltage and delay characteristics comparable to the data path. The computer also specifies additional circuitry to be included in the circuit for indicating a potential speed capability, wherein the additional circuitry is for representing parasitic characteristics in the data path.

Computer program for programming an integrated circuit speed capability indicator

A method and apparatus are disclosed for efficiently doubling a first frequency of a first clock signal. A second clock signal at a second frequency is generated by dividing the first frequency of the first clock signal by two, such that the second frequency is half of the first frequency and a duty cycle of the second clock signal is 50%. Also, a set of phase-delayed clock signals is generated in response to the second clock signal such that the set of phase-delayed clock signals are delayed in phase with respect to the second clock signal. Further, the set of phase-delayed clock signals is combined to generate a third clock signal at a third frequency, such that the third frequency is twice that of the first frequency and a duty cycle of the third clock signal is 50%.

Method and apparatus for synthesizing a clock signal using a compact and low power delay locked loop (DLL)

The present invention relates to a synchronous self timed memory device. The device includes a plurality of memory cells forming a cell array, at least one local decoder interfacing with the cell array, at least one local sense amplifier and at least one local controller. The local sense amplifier interfaces with at least the decoder and cell array, and is adapted to precharge and equalize at least one line coupled thereto. The local controller interfaces with and coordinates the activities of at least the local decoder and sense amplifier. One embodiment of the present invention relates to a memory device comprising a plurality of synchronous controlled global elements and a plurality of self-timed local elements. In this embodiment, at least one of the self-timed local elements interfaces with the synchronous controlled global element.

The present invention relates to a system and method for providing distributed, highly configurable modular predecoding. The method comprising forming a hierarchical memory structure including forming a first portion of the hierarchical memory structure adapted to perform a first layer of address predecoding. The method further comprises forming a second portion of the hierarchical memo structure interacting with at least the first portion and adapted to perform a second layer of address predecoding.

Distributed, highly configurable modular predecoding

In one aspect, the invention describes a mechanism for refreshing multiple memory words (rows) per refresh cycle, the number of simultaneously refreshed rows being programmable by a small number of inputs. In another aspect, the invention discloses a mechanism for refreshing all banks or a programmable number of banks simultaneously in a multi-bank memory. In yet another aspect, the present invention describes a mechanism for refreshing a programmable multiple memory rows and a programmable multiple banks simultaneously.

Programmable refresh scheduler for embedded DRAMs

A system-on-chip (SOC) device or a random access memory (RAM) chip includes a RAM block. The RAM block includes memory cells, each of which has three transistors. Each memory cell is coupled to both a read bit line and a write bit line. A transparent continuous refresh mechanism has been implemented to read the content of a memory cell and re-write it back to the memory cell without disturbing the access (read/write) cycle, making refresh operations transparent to the system level. The continuous refresh mechanism includes a collision detection mechanism to prevent writing and reading the same memory cell at the same time.

Growing community of inventors

Phoenix, AZ, United States of America

Sami Issa