Intel Corporation

Apple Inc.

Samer Nassar

Eyal Fayneh

Sagi Lahav

Lital Levy-Rubin

Inbar Falkov

Elias Nassar

Ofir Degani

Gerard Richard Williams

Rotem Banin

Harshavardhan Kaushikkar

Gaurav Garg

Srinivasa Rangan Sridharan

Per Hakan Hammarlund

Jeff Gonion

Elan Banin

James Vash

Yair Talker

Vijay K Vuppaladadium

Miguel A Corvacho Hernandez

Ramkumar Krithivasan

Roey Grinvald

Techniques are disclosed relating to an I/O agent circuit. The I/O agent circuit may include a memory bank and be coupled to a set of devices. The I/O agent circuit may assign a device of the set of devices to a subdomain of a plurality of subdomains implemented for the memory bank. The I/O agent circuit may store, in that memory bank, a set of transactions of the device in association with the subdomain assigned to the device. The I/O agent circuit may execute the set of transactions such that transactions stored in the memory bank in association with other ones of the plurality of subdomains than the subdomain assigned to the device do not block execution of the set of transactions.

Memory bank with subdomains

Techniques are disclosed relating to an I/O agent circuit. The I/O agent circuit may include one or more queues and a transaction pipeline. The I/O agent circuit may issue, to the transaction pipeline from a queue of the one or more queues, a transaction of a series of transactions enqueued in a particular order. The I/O agent circuit may generate, at the transaction pipeline, a determination to return the transaction to the queue based on a detection of one or more conditions being satisfied. Based on the determination, the I/O agent circuit may reject, at the transaction pipeline, up to a threshold number of transactions that issued from the queue after the transaction issued. The I/O agent circuit may insert the transaction at a head of the queue such that the transaction is enqueued at the queue sequentially first for the series of transactions according to the particular order.

Ensuring transactional ordering in I/O agent

Techniques are disclosed relating to an I/O agent circuit of a computer system. The I/O agent circuit may receive, from a peripheral component, a set of transaction requests to perform a set of read transactions that are directed to one or more of a plurality of cache lines. The I/O agent circuit may issue, to a first memory controller circuit configured to manage access to a first one of the plurality of cache lines, a request for exclusive read ownership of the first cache line such that data of the first cache line is not cached outside of the memory and the I/O agent circuit in a valid state. The I/O agent circuit may receive exclusive read ownership of the first cache line, including receiving the data of the first cache line. The I/O agent circuit may then perform the set of read transactions with respect to the data.

I/O agent

A system is provided which comprises: a first circuitry to generate a first clock signal; and a second circuitry to generate a second clock signal such that: a frequency of the second clock signal is varied over a clock pulse of the first clock signal, and an average of the frequency of the second clock signal over the clock pulse of the first clock signal is substantially maintained at a target frequency.

Method and apparatus to utilize a digital-time-conversion (DTC) based clocking in computing systems

A divider-less fractional digital phase locked loop (PLL) is disclosed and can include a time-to-digital converter (TDC) to receive a reference clock signal and a digitally control oscillator (DCO) clock signal, and generate a phase difference signal based on the reference clock signal and the DCO clock signal. A counter coupled in parallel to the TDC can receive the clock signal and count an output frequency of the clock signal to detect reference noise within the reference signal that is above a threshold. A sampler can sample an output of the counter using a replica of the reference signal, and generate a plurality of samples. A sample selector can select one of the plurality of samples based on the phase difference signal. A digital phase detector (DPD) can generate an output phase measurement based on the phase difference signal and the selected sample of the plurality of samples.

Divider-less fractional PLL architecture

A system includes a digital-to-time converter (DTC) to generate output signals with phase offsets set by a plurality of DTC input values and a time-to-digital converter (TDC) operatively coupled to the DTC, wherein the TDC has a lower resolution than the DTC. The system also includes a processing component operatively coupled to the DTC and the TDC. The processing device, for each of a plurality of TDC thresholds, determines a DTC input value corresponding to a respective TDC threshold. The processing device may then generate a calibration function based on the determined DTC input values and corresponding TDC thresholds.

Fast digital to time converter linearity calibration to improve clock jitter performance

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Nazareth, Israel

Samer Nassar