International Business Machines Corporation

Globalfoundries Inc.

Sameh W Asaad

Bharat Sukhwani

Hong Min

Mathew S Thoennes

Parijat Dube

Mohit Kapur

Roger Moussalli

Balakrishna Raghavendra Iyer

Kevin Wilson Warren

Bernard V Brezzo

Mudhakar Srivatsa

Richard Gerard Hofmann

Ralph E Bellofatto

Robert J Halstead

Michael K Gschwind

Valentina Salapura

Dong Chen

Paul William Coteus

Donald W Schmidt

Michael A Blocksome

Alan G Gara

Joseph D Ratterman

Philip Heidelberger

Adam James Muff

Todd Edward Takken

Martin Ohmacht

Bruce Martin Fleischer

Alexandre E Eichenberger

Thomas M Gooding

Robert William Wisniewski

John A Gunnels

Mark Edwin Giampapa

Burkhard Steinmacher-Burow

Kathryn Mary O'Brien

Mark Gregory Megerian

Matthias Augustin Blumrich

Shawn Anthony Hall

John Kevin O'Brien

Thomas Winters Fox

Chen-Yong Cher

Barry Marshall Trager

Peng Wu

Bengt-Olaf Schneider

Charles David Wait

Sameer Kumar

James Anthony Marcella

Todd Alan Inglett

George L Chiu

Krishnan Sugavanam

Gerard Vincent Kopcsay

Jeffrey John Parker

Robert Matthew Senger

Noel A Eisley

Jaime Humberto Moreno

Rudolf Adriaan Haring

Craig Brian Stunkel

David L Satterfield

Douglas R Miller

Yutaka Sugawara

Amith R Mamidala

Kristan D Davis

Jose R Brunheroto

Donna N Eng Dillenberger

Michael B Mundy

Ernest Nelson Mandese

Matthew Roger Ellavsky

Benjamin D Parker

Robert E Walkup

James Lee Van Oosten

Samuel J Miller

Ruth Janine Poole

Gabor J Dozsa

Peter Boyle

Brant L Knudson

Nicholas R Dono

Norman Christ

Kahn C Evans

William Maupin Stockdell

Alfred Thomas Watson, Iii

Dajung Lee

Brian E Smith

Bulent Abali

Jose A Tierno

Jude A Rivers

Victor V Zyuban

Gong Su

John-David Wellman

Charles Louis Haymes

Matthew S Thoennes

Thomas Roewer

A computer-implemented method, system and computer program product for minimizing hash collisions of composite keys. Each component ('key component') of the composite key is converted into a linear index that uniquely represents that key component. Such a one-to-one mapping reduces the length (i.e., range of values the key component represents) of each component without introducing any collisions thereby effectively resulting in the lossless compression of the individual key components. Such a linear index for each converted key component is stored in a separate lookup memory. A reduced composite key is then created by joining together the linear indices that represent the components of the composite key thereby reducing the total length or domain (i.e., range of values the composite key represents) of the original composite key in a lossless manner. In this manner, by reducing the total length of the composite key, hash collisions of composite keys are minimized.

Minimizing hash collisions of composite keys

Managing hardware function requests incurring variable response latencies is provided. A request for a hardware function is received from a requesting program. The requested hardware function is expected to incur a variable response latency and is implemented as a main hardware function and a retry hardware function. The main hardware function is executed. It is determined whether a fixed response latency of the main hardware function has been exceeded. A response is returned with a retry flag to the requesting program. The retry flag directs the requesting program to issue a request for the retry hardware function after an interval of time. A unique identifier corresponding to the main hardware function is provided to the requesting program.

Non-blocking hardware function request retries to address response latency variabilities

Techniques are provided for data filtering using hardware accelerators. An apparatus comprises a processor, a memory and a plurality of hardware accelerators. The processor is configured to stream data from the memory to a first one of the hardware accelerators and to receive filtered data from a second one of the hardware accelerators. The plurality of hardware accelerators are configured to filter the streamed data utilizing at least one bit vector partitioned across the plurality of hardware accelerators. The hardware accelerators may be field-programmable gate arrays.

Data filtering using a plurality of hardware accelerators

A method, system and computer program product are disclosed for generating clock signals for a cycle accurate FPGA based hardware accelerator used to simulate operations of a device-under-test (DUT). In one embodiment, the DUT includes multiple device clocks generating multiple device clock signals at multiple frequencies and at a defined frequency ratio; and the FPG hardware accelerator includes multiple accelerator clocks generating multiple accelerator clock signals to operate the FPGA hardware accelerator to simulate the operations of the DUT. In one embodiment, operations of the DUT are mapped to the FPGA hardware accelerator, and the accelerator clock signals are generated at multiple frequencies and at the defined frequency ratio of the frequencies of the multiple device clocks, to maintain cycle accuracy between the DUT and the FPGA hardware accelerator. In an embodiment, the FPGA hardware accelerator may be used to control the frequencies of the multiple device clocks.

Generating clock signals for a cycle accurate, cycle reproducible FPGA based hardware accelerator

A method, system and computer program product are disclosed for using a Field Programmable Gate Array (FPGA) to simulate operations of a device under test (DUT). The DUT includes a device memory having a number of input ports, and the FPGA is associated with a target memory having a second number of input ports, the second number being less than the first number. In one embodiment, a given set of inputs is applied to the device memory at a frequency Fd and in a defined cycle of time, and the given set of inputs is applied to the target memory at a frequency Ft. Ft is greater than Fd and cycle accuracy is maintained between the device memory and the target memory. In an embodiment, a cycle accurate model of the DUT memory is created by separating the DUT memory interface protocol from the target memory storage array.

Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator

Embodiments of the invention are directed to a computer-implemented method of memory acceleration. The computer-implemented method includes mapping, by a processor, an array of logic blocks in system memory to an array of logic blocks stored in level 1 (L1) on an accelerator chip, wherein each logic block stores a respective look up table for a function, wherein each function row of a respective look up table stores an output function value and a combination of inputs to the function. The processor determines that a number of instances of request for the output function value from a logic block is less than a first threshold. The processor evicts the function row to a higher level memory.

On-chip logic accelerator

A method of performing an evaluation of a spatial predicates for first and second regions includes receiving a first set of geohashes representing the first region, and receiving a second set of geohashes representing the second region. The method also includes for each geohash within the first set of geohashes: performing a respective pairwise evaluation of a first spatial primitive for the geohash within the first set and each of the geohashes within the second set to produce a set of first binary results corresponding to respective ones of the geohashes within the second set; and combining the set of first binary results using a first Boolean logic operator to produce one of a set of second binary results corresponding to respective ones of the geohashes within the first set. The method further includes combining the set of second binary results using a second Boolean logic operator to produce a third binary result corresponding to the first set of spatial primitives.

Spatial predicates evaluation on geohash-encoded geographical regions

A method of evaluating each of plurality of spatial primitives for a pair of geohashes is disclosed. The method comprises the steps of: detecting which of the pair of geohashes is a shorter geohash and which of the pair of geohashes is a longer geohash; identifying a breakpoint for the pair of geohashes; determining a set of one or more masks each associated with at least one of the pair of geohashes; evaluating a first one of the spatial primitives for the pair of geohashes, the first one of the spatial primitives being a 'contain' spatial primitive; and evaluating at least a second one of the spatial primitives for the pair of geohashes, the at least second one of the spatial primitives being at least one 'touch' spatial primitive.

Embodiments include methods, systems and computer program products for offloading multiple processing operations to an accelerator. Aspects include receiving a database query from an application, performing an analysis on the query, and identifying a plurality of available accelerators. Aspects further include retrieving cost information for one or more templates available on each of the plurality of available accelerators, determining a query execution plan based on the cost information and the analysis on the query, and offloading one or more query operations to at least one of the plurality of accelerators based on the query execution plan.

Scalable acceleration of database query operations

Embodiments include methods, systems and computer program products a for offloading multiple processing operations to an accelerator includes receiving, by a processing device, a database query from an application. The method also includes performing analysis on the database query and selecting an accelerator template from a plurality of accelerator templates based on the analysis of the database query. The method further includes transmitting an indication of the accelerator template to the accelerator and executing at least a portion of the database query on the accelerator.

Accelerating multiple query processing operations

Methods and arrangements for mapping a query operation to an accelerator are provided. The method includes receiving, by a processor, a query operation and determining the design logic of the query operation, receiving a configuration of one or more available accelerators and a design logic of each of the one or more available accelerators, and determining if the query operation can be offloaded to one or more of the one or more available accelerators. Based on a determination that the query operation can be offloaded to one or more of the one or more available accelerators, the method also includes creating software structures to interface with a selected accelerator and executing the query operation on the selected accelerator. Based on a determination that the query operation cannot be offloaded to one or more of the one or more available accelerators, the method further includes executing the query operation in software.

Mapping query operations in database systems to hardware based query accelerators

Growing community of inventors

Briarcliff Manor, NY, United States of America

Sameh W Asaad