Texas Instruments Corporation

Sameh Sameer Rezeq

Robert Bogdan Staszewski

Khurram Waheed

Dirk Leipold

Oren E Eliezer

Jaimin A Mehta

Khurram Muhammad

Chih-Ming Hung

Jayawardan Janardhanan

Nir Tal

Saket Jalan

Ofer Friedman

Sudheer Kumar Vemulapalli

Vasile Zoicas

Yongtao Wang

Prasad Srinivasan

An apparatus and method of linearization of a digitally-controlled pre-power amplifier (DPA) and RF power amplifier (PA) for performing predistortion calibration to compensate for nonlinearlities in the DPA and PA circuits. A predistortion look up table (LUT) stores measured distortion compensation data that is applied to the TX data before being input to the digital-to-frequency converter (DFC), DPA and PA. The on-chip receiver, which is normally inactive during the TX burst in a half-duplex operation, demodulates the RF PA output and uses the digital I/Q RX outputs to perform calibration of the TX pre-distortion tables. A sample of the RF output signal is provided to the receiver chain. While the PA (DPA) code is increasing (or decreasing), the amplitude and phase of the recovered I/Q samples are used to determine the instantaneous value of the AM/AM and AM/PM pre-distortion from which an update to the predistortion tables may be computed.

Linearization and calibration predistortion of a digitally controlled power amplifier

A transmitter using quadrature modulation includes a rectangular to polar converter for converting data symbols into a polar form, where each polar symbol has a magnitude signal and an angle signal. Digital phase modulation circuitry includes an all digital PLL circuit for generating a phase modulated RF carrier signal responsive to the angle signal frequency control word (FCW) and a carrier frequency FCW. A digitally controlled amplifier for amplifying the phase modulated signal is controlled by a digital amplitude control circuitry for controlling the gain of the digitally controlled amplifier responsive to the magnitude signal.

Digital amplitude modulation

A system comprising a pre-power amplifier and a hardware device which is configured to predistort an amplitude input signal by comparing interpolated data places, determined by comparing the input signal with data from a LUT, coming from a LUT with the amplitude input signal and choosing the closest input data place to the amplitude input signal to produce an amplitude predistortion output signal. The LUT contains predistortion data associated with the pre-power amplifier. The amplitude input signal is multiplied and scaled prior to being compared with the data in the LUT. A second LUT is used to predistort a phase input signal and the phase predistortion output signal is combined in the pre-power amplifier with the amplitude predistortion output signal. The system may be implemented in a mobile communications device.

Predistortion system and method based on look up table interpolation

A novel apparatus and method of linearization of a digitally controlled pre-power amplifier (DPA) and RF power amplifier (PA). The mechanism is operative to perform predistortion calibration to compensate for nonlinearities in the DPA and PA circuits. A predistortion look up table (LUT) stores measured distortion compensation data that is applied to the TX data before being input to the digital to frequency converter (DFC), DPA and PA. The mechanism of the invention takes advantage of the on-chip receiver, which is normally inactive during the TX burst in a half-duplex operation, to demodulate the RF PA output and use the digital I/Q RX outputs to perform calibration of the TX pre-distortion tables. Controlled RF coupling is used to provide a sample of the RF output signal that to the receiver chain. The contents of the predistortion LUT are typically updated during the PA power up or down ramp. While the digitally-controlled PA (DPA) code is increasing (or decreasing), the amplitude and phase of the recovered I/Q samples are used to determine the instantaneous value of the AM/AM and AM/PM pre-distortion from which an update to the predistortion tables may be computed.

Linearization of a transmit amplifier

Predistortion methods and apparatus for transmitter linearization in a communication transceiver are disclosed. An example apparatus to linearize a digitally controlled pre-power amplifier included in a transmitter of a communication transceiver disclosed herein comprises a predistorter to predistort an input signal to be processed by the digitally controlled pre-power amplifier, a coupling path within the communication transceiver to couple an output of the digitally controlled pre-power amplifier to an input of a receiver included in the communication transceiver without enabling an output power amplifier stage of a multi-stage power amplifier coupled to an output of the digitally controlled pre-power amplifier, wherein no additional hardware components are required to implement the coupling path within the communication transceiver, and a predistortion evaluator comprising a predistortion calibrator and a predistortion compensator to process data demodulated by the receiver to generate and update predistortion values for use by the predistorter.

Predistortion methods and apparatus for transmitter linearization in a communication transceiver

Method and apparatus for digital amplitude and phase modulation

A novel apparatus for and method of delay alignment between amplitude and phase/frequency modulation paths in a digital polar transmitter. The invention provides a fully digital delay alignment mechanism where better than nanosecond alignment is achieved by accounting for processing delays in the digital circuit modules of the transmitter and by the use of programmable delay elements spread across several clock domains. Tapped delay lines compensate for propagation and settling delays in analog elements such as the DCO, dividers, quad switch, buffers, level shifters and digital pre-power amplifier (DPA). A signal correlative mechanism is provided whereby data from the amplitude and phase/frequency modulation paths to be matched is first interpolated and then cross-correlated to achieve accuracy better than the clock domain of comparison. Within the ADPLL portion of the transmitter, precise alignment of reference and direct point injection points in the ADPLL is provded using multiple clock domains, tapped delay lines and clock adjustment circuits.

Precise delay alignment between amplitude and phase/frequency modulation paths in a digital polar transmitter

A transmitter employing a sigma delta modulator having a noise transfer function adapted to shift quantization noise outside at least one frequency band of interest. A technique is presented to synthesize the controllers within a single-loop sigma delta modulator such that the noise transfer function can be chosen arbitrarily from a family of functions satisfying certain conditions. Using the novel modulator design technique, polar and Cartesian (i.e. quadrature) transmitter structures are supported. A transmitter employing polar transmit modulation is presented that shapes the spectral emissions of the digitally-controlled power amplifier such that they are significantly and sufficiently attenuated in one or more desired frequency bands. Similarly, a transmitter employing Cartesian transmit modulation is presented that shapes the spectral emissions of a hybrid power amplifier such that they are significantly and sufficiently attenuated in one or more desired frequency bands.

Transmitter for wireless applications incorporation spectral emission shaping sigma delta modulator

System and method for creating a time alignment analog notch. An embodiment includes a digital power amplifier coupled to an enable signal line and to a digital control bits bus, and a matching network coupled to the digital power amplifier. The matching network to provide impedance matching and the digital power amplifier to produce a current based on a value on the digital control bits bus. The digital power amplifier comprises a selection circuit and a plurality of transistors. The transistors, controlled by outputs of the selection circuit, provide a current based on the value on the digital control bits bus. The adjustment of a delay between a signal on the enable signal line and the values on the digital control bits bus creates an analog notch at about Fs/2, where Fs is a sampling frequency of a sigma-delta modulator used to modulate data provided to the digital power amplifier.

System and method for a time alignment analog notch

A novel sigma delta amplitude modulator having a noise transfer function adapted to shift quantization noise outside at least one frequency band of interest. In one embodiment, the sigma delta amplitude modulator includes a programmable order low pass stage. In a second embodiment, the sigma delta amplitude modulator incorporates comb filtering wherein each comb filter comprises a plurality of fingers to permit greater programmability in the frequency location of notches. A polar transmitter incorporating the sigma delta amplitude modulator is presented that shapes the spectral emissions of the digitally-controlled power amplifier such that they are significantly and sufficiently attenuated in one or more desired frequency bands.

Spectral emission shaping sigma delta modulator for wireless applications

A novel method and apparatus for a negative contributive offset compensation mechanism for a transmit buffer adapted to compensate for the positive offset generated by higher order sigma-delta modulators used to amplitude modulate the transmit buffer. The positive outputs from the sigma-delta modulator are processed differently than the negative outputs. The inverters associated with the negative outputs in the sigma-delta modulator are removed and the clock signal used to drive the transistors corresponding to the negative outputs is negated or shifted 180 degrees from the clock used to drive the transistors corresponding to the positive outputs. A non-inverted version of the clock is used with the positive outputs and an inverse clock is used with the negative outputs. Use of the inverse clock causes a negative contributive offset to be generated that is added on the second half cycle of each clock. The result is an offset compensated RF output signal having zero offset.

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Dallas, TX, United States of America

Sameh Sameer Rezeq