Texas Instruments Corporation

Sameer P Pendharkar

Marie Denison

Binghua Hu

Philip Leland Hower

Seetharaman Sridhar

Pinghai Hao

Naveen Tipirneni

Guru Mathur

Taylor R Efland

Jungwoo Joh

Yongxi Zhang

John Lin

Sunglyong Kim

Dong Seup Lee

Shanjen Pan

Amitava Chatterjee

James Robert Todd

Jarvis Benjamin Jacobs

Chang Soo Suh

David LaFonteese

Henry Litzmann Edwards

Hideaki Kawahara

Scott Balster

Hiroyuki Tomomatsu

Steven L Merchant

Hiroshi Yamasaki

Jonathan S Brodsky

Robert Steinhoff

Qingfeng Wang

Eugen Mindricelu

Takehito Tamura

Tathagata Chatterjee

Philipp Steinmann

Ming-Yeh Chuang

Vladimir Bolkhovsky

Sridhar Seetharaman

Luigi Colombo

Constantin Bulucea

Alexei Sadovnikov

Robert Allan Neidorff

Archana Venugopal

Filippo Marino

Salvatore Giombanco

Jacek Korec

John P Erdeljac

John Manning Savidge Neilson

Timothy Patrick Pauletti

Chin-Yu Tsai

Dan M Mosher

Zachary K Lee

Sheldon Douglas Haynie

Wayne Tien-Feng Chen

He Lin

Ramanathan Ramani

Milton Lee Buschbom

Yoshikazu Kondo

Bill Alan Wofford

Xinfen Chen

Alex Paikin

Colin Johnson

Louis N Hutter

Abbas Ali

Rick L Wise

Jozef C Mitros

Joe R Trogolo

Srikanth Krishnan

Byron Neville Burgess

Lily Springer

Jeffrey P Smith

William E Grose

Hassan Pooya Forghani-Zadeh

Umamaheswari Aghoram

Roland Bucksch

Reed Wilburn Adams

William E Nehrer

Victor Samuel Sinow

Wen-Hwa M Chu

Haim Horovitz

Tsutomu Kubota

Juergen Wittmann

Robert Graham Shaw

Suhail Murtaza

Seetharaman Sridar

Paul C Mannas

Joseph M Ramirez

Steven L Jensen

Meng-Chia Lee

Peter Chia-cu Mei

Britton Robbins

An electrostatic discharge (ESD) protection structure that provides snapback protections to one or more high voltage circuit components. The ESD protection structure can be integrated along a peripheral region of a high voltage circuit, such as a high side gate driver of a driver circuit. The ESD protection structure includes a bipolar transistor structure interfacing with a PN junction of a high voltage device, which is configured to discharge the ESD current during an ESD event. The bipolar transistor structure has a collector region overlapping the PN junction, a base region embedded with sufficient pinch resistance to launch the snapback protection, and an emitter region for discharging the ESD current.

Electrostatic discharge guard ring with snapback protection

In some examples, a transistor comprises a gallium nitride (GaN) layer; a GaN-based alloy layer having a top side and disposed on the GaN layer, wherein source, drain, and gate contact structures are supported by the GaN layer; and a first doped region positioned in a drain access region and extending from the top side into the GaN layer.

Gallium nitride transistor with a doped region

An electrostatic discharge (ESD) protection structure that provides snapback protections to one or more high voltage circuit components. The ESD protection structure can be integrated along a peripheral region of a high voltage circuit, such as a high side gate driver of a driver circuit. The ESD protection structure includes a p-channel device and an n-channel device. The p-channel device includes an n-type barrier region circumscribing a p-type drain region with an n-type body region. The p-channel device may be positioned adjacent to the n-channel device and a high voltage junction diode.

Electrostatic discharge guard ring with complementary drain extended devices

In some examples, a gallium nitride (GaN)-based transistor, comprises a substrate; a GaN layer supported by the substrate; an aluminum nitride gallium (AlGaN) layer supported by the GaN layer; a p-doped GaN structure supported by the AlGaN layer; and multiple p-doped GaN blocks supported by the AlGaN layer, each of the multiple p-doped GaN blocks physically separated from the remaining multiple p-doped GaN blocks, wherein first and second contours of a two-dimensional electron gas (2DEG) of the GaN-based transistor are at an interface of the AlGaN and GaN layers.

Gallium nitride (GaN) based transistor with multiple p-GaN blocks

A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.

Trench gate trench field plate vertical MOSFET

A photo detector includes a superlattice with an undoped first semiconductor layer including undoped intrinsic semiconductor material, a doped second semiconductor layer having a first conductivity type on the first semiconductor layer, an undoped third semiconductor layer including undoped intrinsic semiconductor material on the second semiconductor layer, and a fourth semiconductor layer having a second opposite conductivity type on the third semiconductor layer, along with a first contact having the first conductivity type in the first, second, third, and fourth semiconductor layers, and a second contact having the second conductivity type and spaced apart from the first contact in the first, second, third, and fourth semiconductor layers. An optical shield on a second shielded portion of a top surface of the fourth semiconductor layer establishes electron and hole lakes. A packaging structure includes an opening that allows light to enter an exposed first portion of the top surface of the fourth semiconductor layer.

Superlattice photo detector

An integrated circuit includes a power transistor having at least one transistor finger that lies within a semiconductor material substrate. Each transistor finger has a source region stripe and a substantially parallel drain region stripe. A gate structure lies between the source region stripe and the drain region stripe and has a plurality of fingers that extend over the source region stripe. Contacts are formed that connect to the fingers of the gate structure over thick oxide islands in the source region stripes. A conductive gate runner is connected to the contacts of the gate layer structure over the thick oxide islands in the source region stripe.

Laterally diffused metal oxide semiconductor with gate poly contact within source window

An integrated circuit includes an extended drain MOS transistor with parallel alternating active gap drift regions and field gap drift regions. The extended drain MOS transistor includes a gate having field plates over the field gap drift regions. The extended drain MOS transistor may be formed in a symmetric nested configuration. A process for forming an integrated circuit containing an extended drain MOS transistor provides parallel alternating active gap drift regions and field gap drift regions with a gate having field plates over the field gap drift regions.

Hybrid active-field gap extended drain MOS transistor

Described examples include an integrated circuit having a semiconductor substrate. The integrated circuit has a transistor that includes a buried layer having within the substrate, the buried layer defining a drift region between the buried layer and the top surface and a body region in the substrate extending from the buried layer to the surface of the substrate. The transistor also having a source formed in the body region, a drain extending from the buried layer to the surface of the substrate, a drift well extending from the buried layer toward the top surface and extending from the body region to the drain, a drift surface layer located between the drift well and the top, and a gate proximate to the surface of the substrate at the body region.

Drain-extended transistor

A transistor device includes a field plate that extends from a source runner layer and/or a source contact layer. The field plate can be coplanar with and/or below a gate runner layer. The gate runner layer is routed away from a region directly above the gate metal layer by a gate bridge, such that the field plate can extend directly above the gate metal layer without being interfered by the gate runner layer. Coplanar with the source runner layer or the source contact layer, the field plate is positioned close to the channel region, which helps reduce its parasitic capacitance. By vertically overlapping the metal gate layer and the field plate, the disclosed HEMT device may achieve significant size efficiency without additional routings.

Transistor with source field plates and non-overlapping gate runner layers

A device includes a laterally diffused MOSFET, which in turn includes n-type source and drain regions in a p-type semiconductor substrate. A gate electrode is located over the semiconductor substrate between the source region and the drain region. An isolation region is laterally spaced apart from the source region, and is bounded by an n-type buried layer and an n-type well region that reaches from a surface of the substrate to the buried layer. A p-type doped region and an n-type doped region are disposed within the isolation region, the p-type doped region and the n-type doped region forming a diode. A first conductive path connects the n-type doped region to the source region, and a second conductive path connects the p-type doped region to the gate electrode.

High voltage lateral junction diode device

A semiconductor device includes a MOS transistor located within a semiconductor substrate of a first conductivity type. The transistor includes a body well located between a drain well and a substrate contact well. A buried voltage blocking region of a second conductivity type is located within the substrate and is connected to the body well. The buried voltage blocking region extends toward the substrate contact well, with an unmodified portion of the substrate remaining between the voltage blocking region and the substrate contact well.

High-voltage drain expended MOS transistor

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Richardson, TX, United States of America

Sameer P Pendharkar