Texas Instruments Corporation

L-3 Communications Corporation

Sameer Kumar Ajmera

Stephan Grunow

Satyavolu Srinivas Papa Rao

Changming Jin

Phillip D Matz

Manoj Mehrotra

Patricia Beauregard Smith

Darius Lammont Crenshaw

Puneet Kohli

Jin Zhao

Tae S Kim

Kenneth D Brennan

Athanasios John Syllaios

Trace Quentin Hurd

Ju-Ai Ruan

Somit Joshi

Anand J Reddy

Montray Leavy

Michael F Taylor

Edward Raymond Engbrecht

Yuri E Solomentsev

A center region of conductive material/s may be disposed or 'sandwiched' between transition regions of relatively lower conductivity materials to provide substantially low defect density interfaces for the sandwiched material. The center region and surrounding transition regions may in turn be disposed or sandwiched between dielectric insulative material to form a sandwiched and transitioned device structure. The center region of such a sandwiched structure may be implemented, for example, as a device layer such as conductive microbolometer layer for a microbolometer detector structure.

Transitioned film growth for conductive semiconductor materials

A method of forming a semiconductor device including forming a low-k dielectric material over a substrate, depositing a liner on a portion of the low-k dielectric material, and exposing the liner to a plasma. The method also includes depositing a layer over the liner.

N2 based plasma treatment for enhanced sidewall smoothing and pore sealing of porous low-k dielectric films

The density of components in integrated circuits (ICs) is increasing with time. The density of heat generated by the components is similarly increasing. Maintaining the temperature of the components at reliable operating levels requires increased thermal transfer rates from the components to the IC package exterior. Dielectric materials used in interconnect regions have lower thermal conductivity than silicon dioxide. This invention comprises a heat pipe located in the interconnect region of an IC to transfer heat generated by components in the IC substrate to metal plugs located on the top surface of the IC, where the heat is easily conducted to the exterior of the IC package. Refinements such as a wicking liner or reticulated inner surface will increase the thermal transfer efficiency of the heat pipe. Strengthening elements in the interior of the heat pipe will provide robustness to mechanical stress during IC manufacture.

Method of fabrication of on-chip heat pipes and ancillary heat transfer components

One aspect of the invention provides a method of forming a semiconductor device (). One aspect includes forming transistors () on a semiconductor substrate (), forming a first interlevel dielectric layer () over the transistors (), and forming metal interconnects () within the first interlevel dielectric layer (). A carbon-containing gas is used to form a silicon carbon nitride (SiCN) layer () over the metal interconnects () and the first interlevel dielectric layer () within a deposition tool. An adhesion layer () is formed on the SiCN layer (), within the deposition tool, by discontinuing a flow of the carbon-containing gas within the deposition chamber. A second interlevel dielectric layer () is formed over the adhesion layer ().

Semiconductor device having improved adhesion and reduced blistering between etch stop layer and dielectric layer

The invention provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, among others, may include forming one or more layers of material within an opening in a substrate, the opening and the one or more layers forming at least a portion of an isolation structure, and subjecting at least one of the one or more layers to an energy beam treatment, the energy beam treatment configured to change a stress of the one or more layers subjected thereto, and thus change a stress in the substrate.

Method for manufacturing an isolation structure using an energy beam treatment

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The present invention provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, among other steps, may include forming a gate structure over a substrate, forming at least a portion of gate sidewall spacers proximate sidewalls of the gate structure, and subjecting the at least a portion of the gate sidewall spacers to an energy beam treatment, the energy beam treatment configured to change a stress of the at least a portion of the gate sidewall spacers, and thus change a stress in the substrate therebelow.

Method for manufacturing a gate sidewall spacer using an energy beam treatment

A device employs damascene layers with a pore sealing liner and includes a semiconductor body. A metal interconnect layer comprising a metal interconnect is formed over the semiconductor body. A dielectric layer is formed over the metal interconnect layer. A conductive trench feature and a conductive via feature are formed in the dielectric layer. A pore sealing liner is formed only along sidewall of the conductive via feature and along sidewalls and bottom surfaces of the conductive trench feature. The pore sealing liner is not substantially present along a bottom surface of the conductive via feature.

Integration of pore sealing liner into dual-damascene methods and devices

The formation of a MIM (metal insulator metal) capacitor () and concurrent formation of a resistor () is disclosed. A copper diffusion barrier () is formed over a copper deposition () that serves as a bottom electrode () of the capacitor (). The copper diffusion barrier () mitigates unwanted diffusion of copper from the copper deposition (), and is formed via electro-less deposition such that little to none of the barrier material is deposited at locations other than over a top surface () of the deposition of copper/bottom electrode. Subsequently, layers of dielectric () and conductive () materials are applied to form a dielectric () and top electrode () of the MIM capacitor (), respectively, where the layer of conductive top electrode material () also functions to concurrently develop the resistor () on the same chip as the capacitor ().

Single mask MIM capacitor and resistor with in trench copper drift barrier

A method () of forming a MIM (metal insulator metal) capacitor is disclosed whereby adverse affects associated with copper diffusion are mitigated even as the capacitor is scaled down. A layer of bottom electrode/copper diffusion barrier material () is formed () within an aperture () wherein the capacitor () is to be defined. The bottom electrode layer () is formed via a directional process so that a horizontal aspect () of the layer () is formed over a metal () at a bottom of the aperture () to a thickness () that is greater than a thickness () of a sidewall aspect () of the layer () formed upon sidewalls () of the aperture (). Accordingly, the thinner sidewall aspects () are removed during an etching act () while some of the thicker horizontal aspect () remains. A layer of capacitor dielectric material () is then conformally formed () into the apertureand over the horizontal aspect (). A layer of top electrode material () is then conformally formed () over the layer of capacitor dielectric material () to complete the capacitor stack ().

Metal insulator metal (MIM) capacitor fabrication with sidewall barrier removal aspect

A trench and via structure is formed in a low k dielectric layer () formed over a silicon substrate (). Super critical COand a first silylization agent are used to form a chemically bonded high density surface layer (). Silanol species are removed from the low k dielectric layer () using super critical COand a second silylization agent. A barrier layer () and copper () are used to fill the trench and via structure.

Growing community of inventors

Richardson, TX, United States of America

Sameer Kumar Ajmera