International Business Machines Corporation

Globalfoundries Inc.

Accenture Global Solutions Limited

Sameer Kumar

Philip Heidelberger

Michael A Blocksome

Dong Chen

Jeffrey John Parker

Joseph D Ratterman

Burkhard Steinmacher-Burow

Amith R Mamidala

Gabor J Dozsa

Douglas R Miller

Martin Ohmacht

Robert William Wisniewski

Mark Edwin Giampapa

Robert Matthew Senger

Yutaka Sugawara

Valentina Salapura

Brian E Smith

Thomas M Gooding

Noel A Eisley

Michael K Gschwind

Charles J Archer

Paul William Coteus

Alan G Gara

Adam James Muff

Todd Edward Takken

Bruce Martin Fleischer

Alexandre E Eichenberger

John A Gunnels

Kathryn Mary O'Brien

Mark Gregory Megerian

Sameh W Asaad

Matthias Augustin Blumrich

Shawn Anthony Hall

John Kevin O'Brien

Thomas Winters Fox

Chen-Yong Cher

Barry Marshall Trager

Peng Wu

Charles David Wait

James Anthony Marcella

Todd Alan Inglett

George L Chiu

Krishnan Sugavanam

Gerard Vincent Kopcsay

Yogish Sabharwal

Rudolf Adriaan Haring

Craig Brian Stunkel

David L Satterfield

Kristan D Davis

Jose R Brunheroto

Michael B Mundy

Matthew Roger Ellavsky

Robert E Walkup

Nikhil Jain

James Lee Van Oosten

Samuel J Miller

Ruth Janine Poole

Thomas George

Brant L Knudson

Peter Boyle

Ralph E Bellofatto

Norman Christ

Kahn C Evans

William Maupin Stockdell

Alfred Thomas Watson, Iii

Anshul Mittal

Dong Chen Chen

Pavlos Michael Vranas

Bryan Savoye Rosenburg

Sameh Sherif Sharkawi

Bob Richard Cernohous

Gheorghe Almasi

Vijay Anand Saraswat

Jayant Swamy

Srinivasan Ramaswamy

Aniruddha Ray

Vivek Kumar Pandey

Sanjaykumar Joshi

Rajeev John

Vismay Vyas

Priya Das

Satyaki Bhattacharya

Alana Gara

Philp Heidelberger

Examples for enhancing veracity of data are described herein. Data from a repository may be received based on a data receiving rule. From the received data, a first dataset may be generated using statistical modeling. Also, a first data veracity score for the first dataset is generated which is indicative of a degree of usability of the dataset. Another aspect relates to identifying an anomaly in the first dataset, the corrector, for each anomaly, to identify a correction technique from amongst a plurality of correction techniques. Further, a second dataset is generated using the identified correction technique having second data veracity score higher than the first data veracity score.

Data accuracy using natural language processing

In a L&#xd7;M&#xd7;N 3D torus network of computer nodes, a 2-dimensional plane comprising M&#xd7;N torus network of nodes mapped into M/2 meshes&#xd7;2*N torus network of nodes. N can be k*M, k is an integer greater than zero, and M and N are even numbers. Each of M/2 mesh of the 2*N torus is contiguous in the 2D plane. Mapping is performed for each of the L planes of the L&#xd7;M&#xd7;N 3D torus network. The M/2 meshes are combined with a remaining torus network dimension comprising L planes, the combining creating another 2*N pattern, wherein an L*M/2&#xd7;2*N communication pattern is created. Application entities are executed according to the mapped L*M/2&#xd7;2*N communication pattern.

Mapping 2-dimensional meshes on 3-dimensional torus

Methods and systems for monitoring remote transmissions of messages among a plurality of nodes are described. A processing element in a first node may allocate a sequence number to a request to read and/or update data in a second node. The processing element may be different from main processors of the first node. The processing element may send the message and the sequence number to the second node. The processing element may modify a status of the sequence number to an active state, indicating a transmission of the message is pending. The processing element may, in response to a response from the second node, modify the status of the sequence number to an inactive state, indicating a completed transmission of the message. The processing element may, in response to no response from the second node within a time period, resend the message and the sequence number to the second node.

Reliability processing of remote direct memory access

A shared memory maintained by sender processes stores a sequence number counter per destination process. A sender process increments the sequence number counter in the shared memory in sending a message to a destination process. The sender process sends a data packet comprising the message and at least a sequence number specified by the sequence number counter. All of the sender processes share a sequence number counter per destination process, each of the sender processes incrementing the sequence number counter in sending a respective message. Receiver processes run on the hardware processor, each of the receiver processes maintaining a local memory counter on the memory, the local memory counter associated with a sending node. The local memory counter stores a sequence number of a message received from the sending node. The receiver process delivers incoming data packets ordered by sequence numbers of the data packets.

Reduced number of counters for reliable messaging

Techniques are disclosed for efficient handling of messages in computing systems that include tag matching capable hardware. A message management module provides for handling message events including application receives and channel notifications such that hardware tag matching can continuously run in hardware channels, such as network adapters. When the message event is an application receive the message management module adds the application receive to a tracking queue and determines if the application receive can be posted to a hardware channel capable of tag matching. When the message event is a channel notification, the message management module determines a message action using the message tracking queue and the information in the channel notification.

Messaging software management for network devices supporting hardware tag matching

The example computer-implemented method may comprise computing, by a generator processor on each of a plurality of learners, a gradient for a mini-batch using a current weight at each of the plurality of learners. The method may also comprise generating, by the generator processor on each of the plurality of learners, a plurality of triples, wherein each of the triples comprises the gradient, the weight index of the current weights used to compute the gradient, and a mass of the gradient. The method may further comprise performing, by a reconciler processor on each of the plurality of learners, an allreduce operation on the plurality of triples to obtain an allreduced triple sequence. Additionally, the method may comprise updating, by the reconciler processor on each of the plurality of learners, the current weight at each of the plurality of learners to a new current weight using the allreduced triple sequence.

Asynchronous stochastic gradient descent

A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaflop-scale includes node architectures based upon System-On-a-Chip technology, where each processing node comprises a single Application Specific Integrated Circuit (ASIC). The ASIC nodes are interconnected by a five dimensional torus network that optimally maximize the throughput of packet communications between nodes and minimize latency. The network implements collective network and a global asynchronous network that provides global barrier and notification functions. Integrated in the node design include a list-based prefetcher. The memory system implements transaction memory, thread level speculation, and multiversioning cache that improves soft error rate at the same time and supports DMA functionality allowing for parallel processing message-passing.

Multi-petascale highly efficient parallel supercomputer

A method (and structure) for improving efficiency in a multiprocessor system including a plurality of processor nodes interconnected in a multidimensional array, each processor node including a processor, an associated memory device, and an associated inter-nodal interface device for exchange of data with other nodes. Each processor can implement a broadcast procedure as an initiator node, using a format that permits inter-nodal interface devices at each node receiving a broadcast instruction packet to process the received broadcast instruction packet without using processing resources of the processor at the receiving node. Each inter-nodal interface device in each node can implement the broadcast procedure without using processing resources of the processor associated with the receiving node.

Mechanism to extend the remote get to do async rectangle broadcast on a rectangle with wild cards in the packet header

Methods and arrangements for performing synchronized collective operations. Communication calls are accepted from at least two distinct processor groups. Edge disjoint spanning paths are created over a collective comprising the processor groups, and the spanning paths are assigned to the processor groups to facilitate communication within each processor group.

Performing synchronized collective operations over multiple process groups

A system and method for enhancing barrier collective synchronization on a computer system comprises a computer system including a data storage device. The computer system includes a program stored in the data storage device and steps of the program being executed by a processor. The system includes providing a plurality of communicators for storing state information for a barrier algorithm. Each communicator designates a master core in a multi-processor environment of the computer system. The system allocates or designates one counter for each of a plurality of threads. The system configures a table with a number of entries equal to the maximum number of threads. The system sets a table entry with an ID associated with a communicator when a process thread initiates a collective. The system determines an allocated or designated counter by searching entries in the table.

Mechanism of supporting sub-communicator collectives with o(64) counters as opposed to one counter for each sub-communicator

Processing posted receive commands in a parallel computer, including: posting, by a parallel process of a compute node, a receive command, the receive command including a set of parameters excluding the receive command from being directed among parallel posted receive queues; flattening the parallel unexpected message queues into a single unexpected message queue; determining whether the posted receive command is satisfied by an entry in the single unexpected message queue; if the posted receive command is satisfied by an entry in the single unexpected message queue, processing the posted receive command; if the posted receive command is not satisfied by an entry in the single unexpected message queue: flattening the parallel posted receive queues into a single posted receive queue; and storing the posted receive command in the single posted receive queue.

Processing posted receive commands in a parallel computer

A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.

A system, method and computer program product for performing various store-operate instructions in a parallel computing environment that includes a plurality of processors and at least one cache memory device. A queue in the system receives, from a processor, a store-operate instruction that specifies under which condition a cache coherence operation is to be invoked. A hardware unit in the system runs the received store-operate instruction. The hardware unit evaluates whether a result of the running the received store-operate instruction satisfies the condition. The hardware unit invokes a cache coherence operation on a cache memory address associated with the received store-operate instruction if the result satisfies the condition. Otherwise, the hardware unit does not invoke the cache coherence operation on the cache memory device.

Store-operate-coherence-on-value

Growing community of inventors

White Plains, NY, United States of America

Sameer Kumar