Intel Corporation

Sameer Kp

Prasoonkumar Surti

Karthik Vaidyanathan

Atsuo Kuwahara

Hugues Labbe

Jonathan Kennedy

Abhishek R Appu

Joydeep Ray

Murali Ramadoss

Michael Apodaca

Abhishek Venkatesh

Altug Koker

Balaji Vembu

Ankur N Shah

Sagar C Pawar

Ravindra A Babu

Satyanantha Ramagopal Musunuri

Sashank Ms

Kalyan K Kaipa

Vijayakumar Balakrishnan

Travis T Schluessler

Rajesh M Sankaran

Kun Tian

David M Puffer

Pattabhiraman K

Niranjan L Cooray

David J Cowperthwaite

Susanta Bhattacharjee

Satyeshwar Singh

Vasanth Ranganathan

Nikos Kaburlasos

Adam T Lake

Carsten Benthin

John H Feit

Selvakumar Panneer

Tomer Bar-On

Jacek Kwiatkowski

Mrinalini Attaluri

Kai Xiao

Gabor Liktor

Seh Kwa

Nausheen Ansari

Jeffery S Boles

Andrew T Lauritzen

David M Cimini

Slawomir Grajewski

Bharath Kumar

Mallari C Hanchate

Sanjeev Tiwari

Sudhir Tonse

Meeta Mishra

Ganesh R St

Jeffrey S Boles

Sridhar Rajagopal

Anila Degwekar

When the speed of head movement exceeds the processing capability of the system, a reduced depiction is displayed. As one example, the resolution may be reduced using coarse pixel shading in order to create a new depiction at the speed of head movement. In accordance with another embodiment, only the region the user is looking at is processed in full resolution and the remainder of the depiction is processed at lower resolution. In still another embodiment, the background depictions may be blurred or grayed out to reduce processing time.

Compensating for high head movement in head-mounted displays

Disclosed herein are techniques to coordinate power management between a platform and a panel. Provided are apparatuses, techniques, and circuitry to determine whether to initiate power management features in a panel and send a signal from a platform to the panel including an indication that no frame updates are expected and power management functions can be initiated.

Co-existence of full frame and partial frame idle image updates

Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.

Controlling coarse pixel size from a stencil buffer

An apparatus and method are described for implementing memory management in a graphics processing system. For example, one embodiment of an apparatus comprises: a first plurality of graphics processing resources to execute graphics commands and process graphics data; a first memory management unit (MMU) to communicatively couple the first plurality of graphics processing resources to a system-level MMU to access a system memory; a second plurality of graphics processing resources to execute graphics commands and process graphics data; a second MMU to communicatively couple the second plurality of graphics processing resources to the first MMU; wherein the first MMU is configured as a master MMU having a direct connection to the system-level MMU and the second MMU comprises a slave MMU configured to send memory transactions to the first MMU, the first MMU either servicing a memory transaction or sending the memory transaction to the system-level MMU on behalf of the second MMU.

Apparatus and method for memory management in a graphics processing environment

The systems, apparatuses and methods may provide a way to adaptively process and aggressively cull geometry data. Systems, apparatuses and methods may provide for processing, by a positional only shading pipeline (POSH), geometry data including surface triangles for a digital representation of a scene. More particularly, systems, apparatuses and methods may provide a way to identify surface triangles in one or more exclusion zones and non-exclusion zones, and cull surface triangles in one or more exclusion zones.

Positional only shading pipeline (POSH) geometry data processing with coarse Z buffer

Systems, apparatuses and methods may provide for technology that assigns a first shading rate to a first region of a frame. The technology further assigns a second shading rate to a second region of the frame. The first shading rate indicates that the first region will be rendered at a first resolution, and the second shading rate indicates that the second region will be rendered at a second resolution less than the first resolution. The first and second shading rates are associated with a selection based on a motion vector that corresponds to motion of an object. The object is rendered as part of a scene that includes the first region rendered at the first resolution and the second region rendered at the second resolution.

Motion biased foveated renderer

Two extended embedded Display Port displays may be enabled by using a single set of panel power sequencing (PPS) signals from a chipset to enable the two embedded Display Port panels. To enhance the user experience, the backlight module brightness is controlled by making use of a pin available on a system on a chip (SOC) and modification of drivers. This helps to save power when only one panel is used. When both panels are used simultaneously, power savings can be achieved by using backlight control signals.

Enabling a chipset that supports a single display to support dual display

Growing community of inventors

Bengaluru, India

Sameer Kp