Intel Corporation

Sameer Jayanta Joglekar

Rui Ma

Mark Armstrong

Ayan Kar

Kalyan C Kolluru

Nicholas A Thomson

Akm A Ahsan

Hyuk Ju Ryu

Sayan Saha

Disclosed herein are transistor arrangements of field-effect transistors with dual thickness gate dielectrics. An example transistor arrangement includes a semiconductor channel material, a source region and a drain region, provided in the semiconductor material, and a gate stack provided over a portion of the semiconductor material that is between the source region and the drain region. The gate stack has a thinner gate dielectric in a portion that is closer to the source region and a thicker gate dielectric in a portion that is closer to the drain region, which may effectively realize tunable ballast resistance integrated with the transistor arrangement and may help increase the breakdown voltage and/or decrease the gate leakage of the transistor.

Field-effect transistors with dual thickness gate dielectrics

Growing community of inventors

Hillsboro, OR, United States of America

Sameer Jayanta Joglekar