Conexant Systems, Inc.

Mindspeed Technologies, Inc.

Sameer I Bidichandani

Moataz A Mohamed

Sumant Ramprasad

In one disclosed embodiment an instruction loop having at least one instruction is identified. For example, each instruction can be a VLIW packet comprised of several individual instructions. The instructions of the instruction loop are fetched from a program memory. The instructions are then stored in a register queue. For example, the register queue can be implemented with a head pointer which is adjusted to select a register in which to write each instruction that is fetched. It is then determined whether the processor requires execution of the instruction loop, for example, by checking a program counter (PC) value corresponding to each instruction. When the processor requires execution of the instruction loop, the instructions are output from the register queue. For example, the register queue can be implemented with an access pointer which is adjusted to select a register from which to output each instruction that is required.

Method for reducing power when fetching instructions in a processor and related apparatus

A circuit and method for reducing power in a memory, such as an instruction cache, having a number of blocks, are disclosed. A power reduction signal (also called a &ldquo;same block&rdquo; signal) is generated. The power reduction signal indicates whether a subsequent instruction to be fetched from an instruction cache belongs in the same block as a previous instruction fetched from the same instruction cache. When the subsequent instruction belongs to the same block as the previous instruction, there is no need to perform a tag read or an instruction read from an instruction cache other than the same instruction cache which contains the block to which the subsequent instruction belongs, whereby a tag from a tag memory bank is not read when the power reduction signal is in a first logical state.

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Tustin, CA, United States of America

Sameer I Bidichandani