Other

Nvidia Corporation

Transmeta Corporation

Intellectual Ventures Holding 81 LLC

Sameer Halepete

Andrew Read

Keith Klayman

H Peter Anvin

Zongjian Chen

Godfrey P D'Souza

Marc Fleischmann

Thomas R Lawrence

Stuart F Oberman

Ming Yiu Siu

Steven T Walther

Scott B Kuusinen

A method for reducing power utilized by a processor including the steps of determining that a processor is transitioning from a computing mode to a mode is which system clock to the processor is disabled, and reducing core voltage to the processor to a value sufficient to maintain state during the mode in which system clock is disabled.

Saving power when in or transitioning to a static mode of a processor by using feedback-configured voltage regulator

Saving power when in or transitioning to a static mode of a processor

A method for controlling the power used by a computer including the steps of measuring the operating characteristics of a central processor of the computer, determining when the operating characteristics of the central processor are significantly different than required by the operations being conducted, and changing the operating characteristics of the central processor to a level commensurate with the operations being conducted.

Adaptive power control

A method for reducing power utilized by a processor including determining that a processor is transitioning from a computer mode to a mode in which system clock to the processor is disabled, and reducing core voltage to the processor to a value sufficient to maintain state during the mode in which system clock is disabled.

Transitioning to and from a sleep state of a processor

Methods, apparatuses, and systems are presented for performing instructions using multiple execution units in a graphics processing unit involving issuing an instruction for P executions of the instruction wherein each execution uses different data, P being a positive integer, the instruction being issued based on a first clock having a first clock rate, operating Q execution units to achieve the P executions of the instruction, Q being a positive integer less than P and greater than one, each of the execution units being operated based on a second clock having a second clock rate higher than the first clock rate of the first clock, and wherein the second clock rate of the second clock is equal to the first clock rate of the first clock multiplied by the ratio P/Q.

Executing an SIMD instruction requiring P operations on an execution unit that performs Q operations at a time (Q&#x3c;P)

A delayed bitline leakage compensation circuit for memory devices is disclosed. The delayed bitline leakage compensation circuit includes a bitline leakage model circuit for modeling discharge of a bitline by leakage current in a read operation. It further has a delayed charge signal generator for generating a delayed charge signal in response to the bitline leakage model circuit discharging to approximately a discharge threshold. The delayed charge signal generator is deactivated if the bitline is discharged by a selected memory cell. Moreover, the delayed bitline leakage compensation circuit includes a delayed charge circuit for charging the bitline in response to the delayed charge signal.

Delayed bitline leakage compensation circuit for memory devices

Growing community of inventors

San Jose, CA, United States of America

Sameer Halepete