Intel Corporation

Mcafee, Inc.

Sameer Desai

Hisham Shafi

Ravi L Sahita

Ittai Anati

Alexander Gendler

Nadav Shulman

Michael Mishaeli

Gideon Gerzon

Ofer Levy

Yuriy Bulygin

Ariel Berkovits

Andrew A Furtak

Oleksandr Bazhaniuk

Shani Rehana

Mikhail V Gorobets

In an embodiment, a processor for Return Oriented Programming (ROP) detection includes at least one execution unit; a plurality of event counters, each event counter associated with a unique type of a plurality of types of control transfer events; and a ROP detection unit. The ROP detection unit may be to: adjust a first event counter in response to detection of a first type of control transfer events; in response to a determination that the first event counter exceeds a first threshold, access a first configuration register associated with the first event counter to read configuration data; identify a set of ROP heuristic checks based on the configuration data read from the first configuration register; and perform each ROP heuristic check of the identified set of ROP heuristic checks. Other embodiments are described and claimed.

Detection of return oriented programming attacks in a processor

A method and apparatus for flushing and restoring core memory content to and from, respectively, external memory are described. In one embodiment, the apparatus is an integrated circuit comprising a plurality of processor cores, the plurality of process cores including one core having a first memory operable to store data of the one core, the one core to store data from the first memory to a second memory located externally to the processor in response to receipt of a first indication that the one core is to transition from a first low power idle state to a second low power idle state and receipt of a second indication generated externally from the one core indicating that the one core is to store the data from the first memory to the second memory, locations in the second memory at which the data is stored being accessible by the one core and inaccessible by other processor cores in the IC; and a power management controller coupled to the plurality of cores and located outside the plurality of cores.

Flushing and restoring core memory content to external memory

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Folsom, CA, United States of America

Sameer Desai