Cryptography Research, Inc.

Amazon Technologies, Inc.

Samatha Gummalla

Bryan Jason Wang

Elke De Mulder

Michael Hutter

Winthrop Wu

Joel Patrick Wittenauer

Qinglai Xiao

Ali Rahbar

Nhon Toai Quach

John Charles Wright

Jonathan Kang

Utpal Vijaysinh Solanki

Gururaj Ananthateerta

Ashish Raj

Techniques for providing execution verification at an integrated circuit device are described. The integrated circuit device may include a processor core configured to execute instructions. The integrated circuit device may also include a trace block configured to extract an execution trace from the processor core, the execution trace indicating the instructions that have been executed by the processor core. The integrated circuit device may further include a verification core configured to receive the execution trace from the trace block, extract an address from a control transfer instruction in the execution trace, perform one or more checks on the address, and generate an alarm signal based on the one or more checks.

Security subsystem for execution verification

Technologies for detecting and classifying errors detected in pipelined hardware are described. One device includes a hardware pipeline with a set of pipeline stages. Error detection logic can detect an error in the hardware pipeline, and control logic can classify the error in one of the multiple categories based on a type of the error, a position of the first data in a data stream that triggered the error, and a position of a pipeline stage in which the error is detected. The control logic can perform an error-response action based on the error classification of the error.

Pipelined hardware error classification and handling

A DMA system includes two or more DMA engines that facilitate transfers of data through a shared memory. The DMA engines may operate independently of each other and with different throughputs. A data flow control module controls data flow through the shared memory by tracking status information of data blocks in the shared memory. The data flow control module updates the status information in response to read and write operations to indicate whether each block includes valid data that has not yet been read or if the block has been read and is available for writing. The data flow control module shares the status information with the DMA engines via a side-channel interface to enable the DMA engines to determine which block to write to or read from.

Data flow control module for autonomous flow control of multiple DMA engines

A computing system includes a host device and a root of trust (RoT) device for performing batch encryption and decryption operations facilitated by a direct memory access (DMA) engine. The host device generates a command table for batch processing of a set of address tables that each describe a set of data blocks of a file to be encrypted or decrypted. The DMA engine facilitates a DMA transfer of the command table from the host memory to an RoT memory of the RoT device. The RoT device then performs batch processing of the address tables referenced in the command table. For each address table, the DMA engine copies a set of data blocks from the host memory to the RoT memory, a cryptographic engine encrypts or decrypts the data blocks, and the DMA engine copies the transformed data blocks back to the host memory.

Batch transfer of commands and data in a secure computer system

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Dublin, CA, United States of America

Samatha Gummalla