Qualcomm Incorporated

Samar Asbe

Thomas Zeng

Qazi Bashir

Adam Openshaw

Thomas Philip Speier

Azzedine Touzni

Girish Bhat

Steven Halter

Mahadevamurty Nemani

Olav Haugan

Vipul Gandhi

Ai Li

Paul Richard Ellis

Priyanka Dosi

Suresh Bollapragada

Chris Henroid

Tero M Kukola

Mitchel Allen Humpherys

Daren Hall

Miguel Ballesteros

Shivaprasad Hongal

Priyesh Sanghvi

Vijayakumar Gopalakrishnan

Changjian Gao

Brijen Raval

Richard Wesley Bass

Rengarajan Ragavan

Denis Pochuev

Systems and techniques are provided for identity impersonation in access control systems. For example, a process for identity impersonation in access control systems can include: receiving, at a hardware identity impersonator from a first access domain, a request to make a target region accessible to a second access domain; updating a second access domain identity data structure to include an entry corresponding to the first access domain, the entry comprising an address of the target region and a first access domain identifier; receiving, at the hardware identity impersonator from the second access domain, an access request to access the target region, wherein the access request comprises an address and a second access domain identifier of the second access domain; and transmitting, at the hardware identity impersonator based on the access request, the address and the first access domain identifier to a memory management unit (MMU) of an access control system.

Hardware identity impersonation for target access control

Systems and techniques are provided for establishing a connection. For instance, a process may include receiving, by a first root of trust (C-ROT) of a first chiplet of a plurality of chiplets from a second C-RoT of a second chiplet, a second certificate along with security state information and debug information for the second chiplet; authenticating a security state and a debug state of the second chiplet based on the security state information and the debug information; authenticating the second certificate; and establishing a security boundary with the second chiplet.

Establishing system on chip root of trust from multiple chiplet roots of trust

Resource access control in a system-on-chip ('SoC') may employ an agent executing on a processor of the SoC and a trust management engine of the SoC. The agent, such as, for example, a high-level operating system or a hypervisor, may be configured to allocate a resource comprising a memory region to an access domain and to load a software image associated with the access domain into the memory region. The trust management engine may be configured to lock the resource against access by any entity other than the access domain, to authenticate the software image associated with the access domain, and to initiate booting of the access domain in response to a successful authentication of the software image associated with the access domain.

Access control system and method for isolating mutually distrusting security domains

Systems, methods, and computer programs are disclosed for optimizing headless virtual memory management in a system on chip (SoC) with global translation lookaside buffer shootdown. The SoC comprises an application processor configured to execute a headful virtual machine and one or more SoC processing devices configured to execute a corresponding headless virtual machine. The method comprises issuing a virtual machine mapping command with a headless virtual machine having a first virtual machine identifier. In response to the virtual machine mapping command, a current value stored in a hardware register in the application processor is saved. The first virtual machine identifier associated with the headless virtual machine is loaded into the hardware register. A translation lookaside buffer (TLB) invalidate command is issued while the first virtual machine identifier is loaded in the hardware register. Upon completion of translation lookaside buffer synchronization, the current value is restored to the hardware register.

Optimizing headless virtual machine memory management with global translation lookaside buffer shootdown

In an aspect, an apparatus that includes a first security domain and at least a second security domain obtains, at a virtual machine of the first security domain, a stream identifier associated with the second security domain. The apparatus generates, at the virtual machine of the first security domain, a command to map the stream identifier associated with the second security domain to a first address translation context. The apparatus maps, at a hypervisor device, the first address translation context to a second address translation context that is associated with the second security domain of the stream identifier. The apparatus processes a stream of memory access transactions that includes the stream identifier based on at least the first address translation context or the second address translation context.

Method and apparatus for establishing system-on-chip (SOC) security through memory management unit (MMU) virtualization

Providing hardware-based translation lookaside buffer (TLB) conflict resolution in processor-based systems is disclosed. In this regard, in one aspect, a memory system provides a memory management unit (MMU) and multiple hierarchical page tables, each comprising multiple page table entries comprising corresponding translation preference indicators. The memory system further includes a TLB comprising multiple TLB entries each configured to cache a page table entry. The MMU determines whether a TLB conflict exists between a first TLB entry caching a first page table entry comprising a translation preference indicator that is set and a second TLB entry caching a second page table entry comprising a translation preference indicator that is not set. If so, the MMU selects the first TLB entry for use in a virtual-to-physical address translation operation, based on the translation preference indicator of the first page table entry cached by the first TLB entry being set.

Providing hardware-based translation lookaside buffer (TLB) conflict resolution in processor-based systems

Aspects include apparatuses and methods for secure, fast and normal virtual interrupt direct assignment managing secure and non-secure, virtual and physical interrupts by processor having a plurality of execution environments, including a trusted (secure) and a non-secure execution environment. An interrupt controller may identify a security group value for an interrupt and direct secure interrupts to the trusted execution environment. The interrupt controller may identify a direct assignment value for the non-secure interrupts indicating whether the non-secure interrupt is owned by a high level operating system (HLOS) Guest or a virtual machine manager (VMM), and whether it is a fast or a normal virtual interrupt. The interrupt controller may direct the HLOS Guest owned interrupt to the HLOS Guest while bypassing the VMM. When the HLOS Guest in unavailable, the interrupt may be directed to the VMM to attempt to pass the interrupt to the HLOS Guest until successful.

Secure, fast and normal virtual interrupt direct assignment in a virtualized interrupt controller in a mobile system-on-chip

Disclosed is a method for inheriting a non-secure thread context. In the method, a first secure monitor call associated with a first non-secure thread of a non-secure environment of a processing system is received. A first secure thread is created, in response to the first secure monitor call, that inherits a first interrupt state of the first non-secure thread.

Apparatus and method for inheriting a non-secure thread context

Growing community of inventors

San Diego, CA, United States of America

Samar Asbe