Intel Corporation

Marvell International Limited

Samantha J Edirisooriya

Sujat Jamil

R Frank O'Bleness

Steven J Tu

David E Miner

Hang T Nguyen

Pankaj Kumar

Gregory W Tse

Geetani R Edirisooriya

Roger C Jeppsen

Blaine Monson

Mark A Schmisseur

Robert L Sheffield

Shanker R Nagesh

K L Siva Prasad Gadey N V

Mark Norman Fullerton

Robert Z Papp

A processing system includes a processor and a VM-to-VM communication accelerator circuit comprising a first interface device to support direct memory access (DMA) data transfers by the first VM, a register to store a reference to a primary physical function (PF) associated with the first interface device, wherein the first primary PF is associated with an access control table (ACT) specifying an access permission for the first VM with respect to a second VM, and a direct memory access (DMA) descriptor processing circuit to process, using a working queue associated with the first primary PF, a DMA descriptor referencing a request for a DMA data transfer between the first VM and the second VM, and execute, using the first interface device, the DMA data transfer based on the access permission.

Hardware-based virtual machine communication supporting direct memory access data transfer

This disclosure is directed to a processing device including a memory to store data, processing circuitry to process data, the processing circuitry including a memory controller to control access to the memory and encryption circuitry to encrypt and decrypt data, and I/O circuitry. The I/O circuitry includes an I/O port to write data to a storage device and to read data from the storage device and an enable encryption bit associated with the I/O port, the I/O port to receive a request to read data from the memory, to send a read command to the memory controller with an enable encryption attribute set when the enable encryption bit is set, and to send a read command to the memory controller with the enable encryption attribute not set when the enable encryption bit is not set. The memory controller is configured to get the data from the memory, to forward the data to the I/O port without decrypting the data when the enable encryption attribute is set, and to cause the encryption circuitry to decrypt the data and to forward the decrypted data to the I/O port when the enable encryption attribute is not set.

Enhanced storage encryption with total memory encryption (TME) and multi-key total memory encryption (MKTME)

In one embodiment, an apparatus comprises a processor core and a power control unit. The power control unit is to identify the occurrence of a power loss from a primary power source, instruct the I/O controller to block further write requests from the one or more I/O devices and to send at least one pending write request stored by the I/O controller to the memory controller, and instruct the memory controller to complete at least one pending write request stored by the memory controller and to cause the memory to be placed into a self-refresh mode.

Method and apparatus for completing pending write requests to volatile memory prior to transitioning to self-refresh mode

Hardware-based virtual machine communication

In an embodiment, a processor for invalidating cache entries comprises: at least one processing unit; a processor cache; and direct cache unit. The direct cache unit is to receive, from a first device, a direct read request for data in a first cache entry in the processor cache; determine whether the direct read request is an invalidating read request; in response to a determination that the direct read request is an invalidating read request: send the data in the first cache entry directly from the processor cache to the first device without accessing a main memory; and invalidate the first cache entry in the processor cache. Other embodiments are described and claimed.

Invalidating reads for cache utilization in processors

Method, apparatus, and system of detecting a hot-plug event. The hot-plug event detection may be done in-band or out-of-band. The in-band detection is performed by a state machine and the out-of-band detection is performed by a logic. A circuitry is to detect a hot-plug event when inserting or removing a device from an extension bus of the plurality of extension bus slots. The circuit is to generate a hot-plug message to notify the hot-plug event. The circuitry including the state machine, the logic and a register to provide at least two bits to mask at least two states of the state machine.

Method, apparatus, and system for plugin mechanism of computer extension bus

Non-processor agents, such as bus agents, may directly access processor caches. A coherency protocol ensures that cache coherency is maintained.

Implementing direct access caches in coherent multiprocessors

A method and system for syndrome generation and data recovery is described. The system includes a parity generator coupled to one or more storage devices to generate parity for data recovery. The parity generator includes a first comparator to generate a first parity factor based on data in one or more of the storage devices, a multiplier to multiply data from one or more of the storage devices with a multiplication factor to generate a product, a second comparator coupled to the multiplier to generate a second parity factor based at least in part on the product, and a selector to choose between the first parity factor and the second parity factor.

Method and system for syndrome generation and data recovery

A method and apparatus for power optimized replay. In one embodiment, the method includes the issuance of an instruction selected from a queue. Once issued, the instruction may be enqueued within a recirculation queue if completion of the instruction is blocked by a detected blocking condition. Once enqueued, instructions contained within the recirculation queue may be reissued once a blocking condition of an instruction within the recirculation queue is satisfied. Accordingly, a power optimized replay scheme as described herein optimizes power while retaining the advantages provided by selectively replaying of blocked instructions to improve power efficiency.

Power optimized replay of blocked operations in a pipilined architecture

A bus control system includes N bus agents each having a corresponding bus request delay and M bus agents each having a corresponding bus request delay. A controller determines the bus request delays of the N bus agents and the M bus agents and grants concurrent ownership of a bus to each of the N bus agents and non-concurrent ownership of the bus to each of the M bus agents based on the determination. M and N are integers greater than 1.

Apparatus and method for arbitrating heterogeneous agents in on-chip busses

A method and apparatus for optimizing line writes in cache coherent systems. A new cache line may be allocated without loading data to fill the new cache line when a store buffer coalesces enough stores to fill the cache line. Data may be loaded to fill the line if an insufficient number of stores are coalesced to fill the entire cache line. The cache line may be allocated by initiating a read and invalidate request and asserting a back-off signal to cancel the read if there is an indication that the coalesced stores will fill the cache line.

Method and apparatus for optimizing line writes in cache coherent systems

Apparatus and method for power optimized replay via selective recirculation of instructions

According to one embodiment a method for implementing bufferless DMA controllers using split transaction functionality is presented. One embodiment of the method comprises, generating a write command from a disk controller directed to a destination unit, the write command including an identifier, generating a read command from the disk controller directed to a source unit, the read command including an identifier which matches the identifier in the write command, the source unit transmitting read data on a split transaction bus, the read data including the identifier of the read command, and receiving the read data at the destination unit via the split transaction bus if the identifier of the read data matches the identifier of the write command.

Implementing bufferless direct memory access (DMA) controllers using split transactions

A system, method, and apparatus for a cache memory to support a low power mode of operation.

Growing community of inventors

Tempe, AZ, United States of America

Samantha J Edirisooriya