International Business Machines Corporation

Qualcomm Incorporated

Samantak Gangopadhyay

Vikas Agarwal

Manish Kumar

Francois Ibrahim Atallah

Burt Lee Price

Keith Alan Bowman

Yeshwant Nagaraj Kolla

Hoan Huu Nguyen

Shashank Joshi

Systems and methods relate to a low-dropout voltage (LDO) voltage regulator which receives a maximum supply voltage and provides a regulated voltage to a load, where the load may be a processing core of a multi-core processing system. A leakage current supply source includes a leakage current sensor to determine a leakage current demand of the load of the LDO voltage regulator and a leakage current supply circuit to supply the leakage current demand. In this manner, the leakage current supply source provides current assistance to the LDO voltage regulator, such that the LDO voltage regulator can supply only dynamic current. Thus, headroom voltage of the LDO voltage regulator, which is a difference between the maximum supply voltage and the regulated voltage, can be reduced. Reducing the headroom voltage allows greater number of dynamic voltage and frequency scaling states of the load.

Leakage current supply circuit for reducing low drop-out voltage regulator headroom

Embodiments of the present invention disclose a method, program product, and a logic circuit structure for correcting early-mode timing violations in a digital circuit design. A portion of a digital circuit design is identified having an early-mode timing violation. A logic circuit is identified within the identified portion of a digital circuit design having the early-mode timing violation. At least one input of the identified logic circuit is identified as having the early-mode timing violation. At least one transistor is added to the identified logic circuit, wherein the input of the added at least one transistor is coupled to the identified at least one input of the identified logic circuit, and wherein the addition of the at least one transistor delays the signal received at the identified at least one input to eliminate the early-mode timing violation.

Stacked multiple-input delay gates

An automated method of modifying a semiconductor chip design includes creating a timing analysis of said semiconductor chip design, identifying a plurality of gates in said semiconductor chip design which have either too fast a rising edge or falling edge, for each gate in said plurality of gates adding a stacked transistor to provide delay to the rising or falling edge of the gate. A design structure tangibly embodied in a machine readable medium for designing, manufacturing, or testing an integrated circuit, the design structure includes a CMOS device having a first transistor with a first input, a pair of stacked transistors having a second input, and an output.

Structure for stacked CMOS circuits

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Atlanta, GA, United States of America

Samantak Gangopadhyay