Freescale Semiconductor,inc.

Infineon Technologies Ag

Samaksh Sinha

Kumar Abhishek

Sunny Gupta

Garima Sharda

Manmohan Rana

Nishant Singh Thakur

Kushal Kamal

Niti Gupta

Chin Yeong Koh

Nitin Pant

Trong D Nguyen

Sunny Sharma

Sai Siddharth Pothapragada

Morthala V Narsi Reddy

A clock generator and a method to control an associated system are described. The clock generator (e.g., a PLL) can include a charge pump that can generate a current, and a controller coupled to the charge pump. The controller can determine a characteristic impacting operation of the clock generator and control the charge pump to adjust the current based on the determined characteristic to adjust a bandwidth of the clock generator. The clock generator and method can include adjusting the bandwidth to compensate for variations (e.g. PVT variations) that impact the operation of the clock generator to maintain constant or substantially constant bandwidth independent of such variations.

Adaptive bandwidth systems and methods

Representative implementations of devices and techniques provide analog to digital conversion of time-discrete analog inputs. A redundant binary scaled capacitance arrangement using a successive approximation technique can provide a fast and power efficient ADC, with improved error correction. For example, a successive approximation capacitor arrangement may include multiple arrays of capacitances with binary bit weights. In an implementation, the technique includes processing the capacitances in successive cycles, where each cycle generates a binary error correction code representing greater than one bit of the digital output.

Asynchronous SAR ADC with binary scaled redundancy

An electronic circuit includes a switchable circuit domain that operates in a RUN mode and a STANDBY mode and receives a supply current from a core power supply. A power regulator is connected between the core power supply and the switchable circuit domain to regulate the supply current provided to the switchable circuit domain when the electronic circuit is in the RUN mode. A capacitor is connected between the power regulator and ground and is charged by a refresh circuit when the electronic circuit is in the STANDBY mode. The refresh circuit maintains a voltage across the capacitor when the electronic circuit is in the standby mode, which reduces the time for the electronic circuit to transition from the STANDBY mode to the RUN mode.

Power supply circuit for reduced wake-up time

A power supply that provides a supply voltage to an integrated circuit (IC) includes high and low power regulators and a power management circuit. The high power regulator regulates the supply voltage at a first voltage level and the low power regulator is set to an inactive mode when the IC is in a RUN mode. When the IC transitions from the RUN mode to a STOP mode, the high power regulator stops regulating and the supply voltage is maintained at a second voltage level, while the lower power regulator is set to an active mode for regulating the supply voltage at a third voltage level. A fallback signal is generated when the supply voltage drops below a first threshold value after which the low power regulator is set in the inactive mode and the high power regulator is configured to regulate the supply voltage at a fourth voltage level.

Power supply for integrated circuit

A well-biasing circuit for an integrated circuit (IC) includes a well-bias regulator for providing well-bias voltages (n-well and p-well bias voltages) to well-bias contacts (n-well and p-well bias contacts) of each cell of the IC when the integrated circuit is in STOP and STANDBY modes. A switch is connected between a core power supply and the well-bias contact for connecting and disconnecting the core power supply and the well-bias contact when the IC is in RUN and STOP modes, and STANDBY mode, respectively. A voltage inverter circuit and a CMOS inverter circuit enable and disable the switch when the IC is in the RUN mode, and STOP and STANDBY modes, respectively.

Well-biasing circuit for integrated circuit

A buffer and control circuit for a synchronous memory controller includes first and second differential comparators and control logic. The first differential comparator is provided with positive and negative differential input signals and the second differential comparator is provided with offset positive and negative differential input signals. The first and second differential comparators generate output signals based on magnitudes of the positive and negative differential input signals and the offset positive and negative differential input signals. The control logic generates a reference strobe signal based on the output signals.

Buffer and control circuit for synchronous memory controller

A power management circuit for managing power supplied to an electronic circuit by a core power supply. The electronic circuit includes digital and analog circuit domains and operates in POWER-ON, RUN and STANDBY modes. The power management circuit includes a master state machine that exchanges a handshake signal with the analog circuit domain to monitor the modes of operation and generates first and second configuration signals. The power management circuit enables and disables the analog circuit domain based on the first and second configuration signals. A switch connected to the core power supply and the digital circuit module enables and disables the digital circuit domain based on the second configuration signal.

Power management circuit using two configuration signals to control the power modes of two circuit modules using two crosslinked multiplexers and a level shifter

A system for generating a clock signal includes a phase-locked loop (PLL) and a voltage storage circuit. The PLL includes a voltage-controlled oscillator (VCO) that generates a clock signal based on a control voltage. The voltage storage circuit includes a unity-gain amplifier (UGA) and first, second and third switches. The first switch connects an input terminal of the UGA and an input of the VCO to sample the control voltage before the PLL transitions from RUN mode to STOP mode. The second switch connects the input and output terminals of the UGA to store the sampled control voltage when the PLL is in STOP mode. The third switch connects the output terminal of the UGA to the input terminal of a low pass filter (LPF) to provide the stored control voltage to the LPF when the PLL transitions from the STOP mode to the RUN mode.

System for generating clock signal

A digital logic controller for regulating a voltage of a SoC includes a first input for receiving a reference signal having a first property that is constant over a range of operating conditions of the SoC, and a second input for receiving a second signal that has a second property that is indicative of an operating condition of the SoC. The second property may vary over a range of operating conditions of the SoC. A comparator compares the first and second properties and the digital logic controller, based on the comparison, outputs to a regulation signal to a voltage regulator to regulate the voltage of the SoC at or near a target voltage that is higher than a minimum operating voltage of the SoC.

Digital logic controller for regulating voltage of a system on chip

An analog-to-digital converter (ADC) converts an analog input signal to a digital output signal by sampling an analog input signal to obtain an analog sample and then converting the analog sample to the digital output signal using a successive approximation algorithm. The method decreases ADC conversion time and increases ADC throughput.

Successive approximation analog-to-digital converter

A phase-locked loop (PLL) generates an oscillator signal based on an input reference signal. A voltage-to-current oscillator converts generates the oscillator signal based on a control. A charge pump circuit generates the charge pump current based on an error (feedback) signal. A low pass filter generates the control voltage based on the charge pump current. A capacitor is connected to an input terminal of the low pass filter that is charged to a voltage level of the control voltage by the low pass filter when the PLL is switched OFF. The voltage across the capacitor is buffered and fed back to the low pass filter when the PLL is switched ON, to reduce time taken by the VCO to generate the oscillator signal. The PLL is used in an electronic circuit to reduce the wake-up time of the electronic circuit.

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Samaksh Sinha