Emulex Design & Manufacturing Corporation

Emulex Corporation

Xerox Corporation

Sam S Su

Qing Xue

Hossein Hashemi

Uoc H Nguyen

Peter Mark Fiacco

Bradley Eugene Roach

Li-Fung Cheung

Michael Yu Liu

George Apostol, Jr

Vi Chau

Dan Tarr

Jean Swey Kao

David Bradley Baldwin

Eric David Peel

Stephen Eugene Holness

Danny T Ong

A system with a first random access memory (RAM), a second RAM, a first processor coupled to the first RAM and a second processor coupled to the second RAM. The first RAM is configured to store input/output (I/O) completions from at least two engines. The second RAM is also configured to store I/O completions from at least two engines. When all engines are active, the system writes I/O completions from the engines to the first and second RAMs. The first processor processes I/O completions stored in the first RAM. The second processor processes I/O completions stored in the second RAM.

Supercharge message exchanger

In an embodiment, an initialization extension device may provide an extended initialization period to enable a processor to configure a device, for example, an application specific integrated circuit (ASIC), prior to entering an operating mode. The device may include a number of control registers that may be configured to default settings in a register initialization period commenced in response to a reset signal. The reset signal may also trigger an extension timer to countdown a timer extended initialization period. During the timer extended initialization period, the processor may write an extension control signal, e.g., an extension bit, to a register. An initialization extension unit may maintain the device in an initialization mode during the timer extended initialization period and/or while the register contains the extension control signal. The processor may configure the control registers for one or more operations the device may perform when it enters the operating mode.

Hardware initialization with or without processor intervention

The present invention is directed to a memory data interface for transferring data between a memory device and an integrated circuit, whereby, in accordance with one aspect of the present invention, the memory data interface includes a data selector for selecting and normalizing data from memory devices operating at different data transfer timing, and, in accordance with another aspect of the present invention, the memory data interface is capable of transferring data between a memory device and an integrated circuit having a different bus width than the memory device. In accordance with yet another aspect of the present invention, the memory data interface is capable of transferring data between an integrated circuit and a variety of different memory device having different data bus widths. Finally, in accordance with yet another aspect of the present invention, the memory data interface is capable of transferring data between an integrated circuit and a variety of memory devices having different bus widths and different data transfer timing.

Memory data interface

A system with a first random access memory (RAM), a second RAM, a first processor coupled to the first RAM and a second processor coupled to the second RAM. The first RAM is configured to store input/output (I/O) completions from atleast two engines. The second RAM is also configured to store I/O completions from at least two engines. When all engines are active, the system writes I/O completions from the engines to the first and second RAMs. The first processor processes I/O completions stored in the first RAM. The second processor processes I/O completions stored in the second RAM.

Extension signal generator coupled to an extension timer and an extension register to generate an initialization extension signal

A hub port in a Fiber Channel loop includes a hub data source, a loop initialization data detect circuit, and a loop initialization counter. The hub data source supplies data to the hub port from the Fiber Channel loop. The loop initialization data detect circuit is configured to detect valid loop initialization sequences from an attached node port and the hub data source. The loop initialization counter is configured to increment a count value of the valid loop initialization sequence from the attached node port if the loop initialization sequence from the node port does not match the valid loop initialization sequence from the hub data source. This state indicates that the loop initialization sequence is initiated by the attached node port.

Detecting and counting node port loop initialization origination

A hub port in a Fibre Channel loop for detecting and bypassing attached node ports in an OLD-PORT state is disclosed. The hub port includes a hub data source, a detect circuits, and an output control circuit. The hub data source supplies data to the hub port from a Fibre Channel loop. The detect circuit is configured to detect a valid non-Arbitrated Loop sequence from an attached node port indicating that the node port is in an OLD-PORT state. The output control circuit operates to bypass the node port from the loop when the valid non-Arbitrated Loop sequence is detected.

Old-port node detection and hub port bypass

A hub port in a loop network is disclosed. The hub port includes a hub data source, first and second detect circuits, and a processor. The hub data source supplies data to the hub port from the loop network. The first detect circuit is configured to detect a first sequence from an attached node port establishing a loop circuit. The second sequence from the attached node port indicates to terminate the loop circuit. The processor is configured to receive the first sequence from the first detect circuit. Further, the processor operates to close a detect window and to increment a sequence origination count, if the detect window is open. The second detect circuit is configured to detect the second sequence from the hub data source confirming the termination of the loop circuit.

Detecting and counting open ordered sets originating from an attached node port

A 'virtual FIFO' system for use in buffering data between transacting buses that transfer data at different rates includes a memory device and a controller that partitions the memory device into multiple regions, each of which is configured to operate as a distinct data buffer.

Buffering data that flows between buses operating at different

An elastic bus interface receives and registers an external data transfer signal and generates an internal data transfer signal that always begins at the beginning of the subsequent clock cycle regardless of the time of arrival of the external data transfer signal. By employing a plurality of data output registers in a pipeline and using only the internal data transfer signal, data is fed to a bus so as to ensure that almost a complete clock cycle is available for setup time to accomplish data transfer. The invention can operate with high speed buses using only simple conventional circuitry and modest process geometries requiring only minimal chip area and power.

Elastic bus interface data buffer

An encoder for encoding four bits of uncompressed data in one clock cycle generates one code or in parallel a plurality of codes if the bits can be represented by a code or by a plurality of codes and keeps the bits that can not be represented by a code unaltered. On the following clock cycle, the unaltered bits from the previous clock cycle will be combined with a new set of four bits of data and the cumulative bits will be converted to a code if they can be represented by a code and if they can not be represented by a code, they will be stored until the next clock cycle. The process of storing the cumulative number of bits will be continued until the cumulative number of bits can be represented by a code.

High-speed encoder

A system for changing the source and destination devices of data transfers under software control. Default data transfers are made from numbered source devices to the same-numbered destination devices, the data requests being routed through multiplexers which pair, for example, source 1 with destination 1, source 2 with destination 2, etc. The multiplexer control signals originate in a register which is originally loaded with default control bits. However, in real time, the bits within the control register can be re-loaded to provide outputs other than the default values. Then, the data from a source can be directed to any one of the destination devices.

Circuit for interfacing data busses

A circuit for enabling data transfer between one data bus connected to a number of devices, such as accelerator cards, and a second data bus, such as one found in a computer. The two data busses are connected by a number of FIFO buffers, and an arbitrator selects a source and destination for each packet. The circuit allows the computer to freeze the data in any or all buffers so that it can be inspected and changed if necessary, but only after the entire current packet for the selected buffer or buffers has been transferred.

Circuit for freezing the data in an interface buffer

A method is described for determining readiness of devices in a digital data bus system to transfer data signals. The bus system includes a bus having a clock line for communicating a clock signal, address lines for communicating address signals, data lines for communicating data signals, and control lines for communicating control signals. The bus system also includes a plurality of devices. Each device is connected to the bus and has an address on the bus. At least one device is a source device capable of sending data signals and at least one device is a destination device capable of receiving data signals. A bus controller connects to the bus and controls the bus. The control lines include bus request lines that connect each device to the bus controller for communicating a bus request signal from a device to the bus controller. The bus request signal indicates that the device is ready to send or receive data signals. The bus controller includes matching logic that stores the identities of predetermined pairs of a source device and a destination device between which matching logic will permit the transfer of data signals. The matching logic receives the bus request signals and determines based on the bus request signals whether a particular allowed pair of source and destination devices are ready to send and receive data signals. According to the method, a source device generates a bus request signal on the bus request lines indicating whether the source device is ready to send data signals on the data lines. Next, a destination device generates a bus request signal on the bus request lines indicating whether the destination device is ready to receive data signals on the data lines. Finally, the matching logic receives the bus request signal generated by the source device and the bus request signal generated by the destination device and, provided the pair of destination and source device are a pair allowed to transfer data signals, decides based on the received bus request signals whether the pair of the destination and source devices is ready to send and receive data signals.

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Rowland Hts., CA, United States of America

Sam S Su