Apple Inc.

Sam Ng

Jerome Francis Duluk, Jr

Richard E Hessel

Sushma Shrikant Trivedi

Jack Benkual

Jason Rupert Redgrave

Joseph P Bratt

Emerson S Fang

Vaughn Todd Arnold

Sidong Li

Stephen L Dodgen

Hengwei Hsu

Matthew N Papakipos

Nathan D Tuck

George Cuan

Zhaoyu Gong

Thomas Y Ho

Lindy Fung

Tuan Anh Nguyen

Abbas Rashid

Shun Wai Go

Abraham Mammen

Bo Hong

Joseph P Grass

Albert Suan-Wei Tsay

Thomas Y Yo

A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple?stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.

Deferred shading graphics pipeline processor having advanced features

A deferred shading graphics pipeline processor and method are provided encompassing numerous substructures. Embodiments of the processor and method may include one or more of deferred shading, a tiled frame buffer, and multiple-stage hidden surface removal processing. In the deferred shading graphics pipeline, hidden surface removal is completed before pixel coloring is done. The pipeline processor comprises a command fetch and decode unit, a geometry unit, a mode extraction unit, a sort unit, a setup unit, a cull unit, a mode injection unit, a fragment unit, a texture unit, a Phong lighting unit, a pixel unit, and a backend unit.

Apparatus and methods for rendering 3D graphics images. The apparatus include a port for receiving commands from a graphics application, an output for sending a rendered image to a display and a fragment-operations pipeline, coupled to the port and to the output, the pipeline including a stage for performing a fragment operation on a fragment on a per-pixel basis, as well as a stage for performing a fragment operation on the fragment on a per-sample basis. The stage for performing on a per-pixel basis is one of the following: a scissor-test stage, a stipple-test stage, an alpha-test stage or a colorest stage, and the stage for performing on a per-sample basis is one of the following: a Z-test stage, a blending stage or a dithering stage. The apparatus programmatically selects whether to perform a stencil test on a per-pixel or a per-sample basis and performs the stencil test on the selected basis. The apparatus also programmatically selects pixel samples for per-sample operations, where the sample selections differ with different instances of the same per-sample operation. The apparatus also programmatically selects a set of subdivisions of a pixel as samples for use in the per-sample fragment operation, programmatically assigns different weights to at least two samples in the set and performs the per-sample fragments operation on the fragment using the programmatically selected and differently weighted samples.

Apparatus and method for fragment operations in a 3D-graphics pipeline

Graphics processors and methods are described that encompass numerous substructures including specialized subsystems, subprocessors, devices, architectures, and corresponding procedures. Embodiments of the invention may include one or more of deferred shading, a bled frame buffer, and multiple-stage hidden surface removal processing, as well as other structures and/or procedures. Embodiments of the present invention are designed to provide high-performance 3D graphics with Phong shading, subpixel anti-aliasing, and texture- and bump-mappings.

Graphics processor with deferred shading

Three-dimensional computer graphics systems and methods and more particularly to structure and method for a three-dimensional graphics processor and having other enhanced graphics processing features. In one embodiment the graphics processor is a Deferred Shading Graphics Processor (DSGP) comprising an AGP interface, a command fetch & decode (,), a geometry unit (,), a mode extraction (,) and polygon memory (,), a sort unit (,) and sort memory (,), a setup unit (,), a cull unit (,), a mode injection (,), a fragment unit (,), a texture (,) and texture memory (,) a phong shading (,), a pixel unit (,), a backend unit (,) coupled to a frame buffer (,). Other embodiments need not include all of these functional units, and the structures and methods of these units are applicable to other computational processes and systems as well as deferred and non-deferred shading graphical processors.

Deferred shading graphics pipeline processor

Three-dimensional computer graphics systems and methods and more particularly to structure and method for a three-dimensional graphics processor and having other enhanced graphics processing features. In one embodiment the graphics processor is Deferred Shading Graphics Processor (DSGP) comprising an AGP interface, a command fetch decode (,), a geometry unit (,), a mode extraction (,) and polygon memory (,), a sort unit (,) and sort memory (,), a setup unit (,), a cull unit (,), a mode injection (,), a fragment unit (,), a texture (,) and texture memory (,) a phong shading (,), a pixel unit (,), a backend unit (,) coupled to a frame buffer (,). Other embodiments need not include all of these functional units, and the structures and methods of these units are applicable to other computational processes and systems as well as deferred and non-deferred shading graphical processors.

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Fremont, CA, United States of America

Sam Ng