Hynix Semiconductor Inc.

Skhynix Inc.

Sam Kyu Won

Kwang Ho Baek

Jae Won Cha

Jin Yong Seong

Duck Ju Kim

Cheul Hee Koo

In Ho Kang

Chang Won Yang

Won Kyung Kang

Myung Su Kim

Min Gyu Kim

You Sung Kim

Byung Ryul Kim

Sung Hyun Jung

Min Kyu Kim

A method of operating a semiconductor memory device includes applying a program pulse at least once to each of a plurality of pages; performing a pre-read operation on a reference page among the plurality of pages through an initial test voltage; repeating the pre-read operation by controlling the initial test voltage until a result of the pre-read operation is a pass; setting the initial test voltage of when the result of the pre-read operation is the pass as a reference test voltage; and detecting a defective page among the plurality of pages by performing read operations on the plurality of pages through the reference test voltage.

Semiconductor device and operating method thereof

A semiconductor device includes a memory cell array includes a plurality of memory blocks, each of the memory blocks including a plurality of pages, wherein at least one of the plurality of memory blocks functions as a first storage unit to store a plurality of page addresses associated with the plurality of pages. A second storage unit loads a page address stored in the first storage unit. A control circuit is configured to cancel a program operation if an externally inputted page address is less than or equal to the page address loaded into the second storage unit, and perform the program operation and update the second storage unit with the externally inputted page address if the externally input page address is greater than the page address loaded into the second storage unit.

Semiconductor device and method of operating the same

A memory system includes first to third memory devices each having an input terminal for receiving a token signal and an output terminal for transmitting the token signal, wherein the input terminal of each of the first to third memory devices are connected to the output terminal of another memory device through a ring topology, a subset of the first to third memory devices substantially simultaneously perform an operation of consuming a peak current in response to any one of a plurality of token signals, and each of the first to third memory devices possesses only any one of the plurality of token signals and transmits the other token signals to another memory device.

Token ring architecture based memory system and operating method to optimize current consumption

The present technology relates to an electronic device, and more particularly, to a semiconductor device. The semiconductor device includes a peripheral circuit, a power output line connected to the peripheral circuit and configured to transmit an operation voltage to the peripheral circuit, a current compensator including an OP-amplifier connected to the power output line, and a capacitor connected between an output terminal of the OP-amplifier and the power output line.

Semiconductor device including current compensator

A flash memory device is disclosed. The flash memory device includes a memory cell array configured to have memory cells for storing data, and store initial data in a part of the memory cells, a page buffer circuit configured to have page buffers for providing data to be programmed in the memory cell or reading data from the memory cell, a controller configured to control the page buffer circuit so that the initial data stored in the memory cell array are read when operation of the flash memory device is started, discriminate error of the read initial data, and amend the error of the initial data, and an initial data latching circuit for latching the initial data of which the error is amended by the controller.

Method of operating a flash memory device

A semiconductor memory device and an erase method in the same are disclosed. The semiconductor memory device includes a memory cell array configured to have a cell string in which memory cells are coupled, a block switch configured to switch a global word line and a word line of the memory cell array, a block decoder configured to control the block switch, and a recycle switch configured to use an erase voltage charged in a P-well of the memory cell array as a supply voltage of the block decoder.

Semiconductor memory device and erase method in the same

A semiconductor memory device can improve electrical properties by prohibiting a leakage current, which flows through a memory cell, in such a way as to turn off a drain select transistor, a source select transistor and a side transistor of an unselected memory cell block when the semiconductor memory device operates. The semiconductor memory device includes a memory cell block in which a plurality of memory cells, drain and source select transistors, and side word line transistors are connected in a string structure, a block decoder for outputting a block select signal in response to predecoded address signals and controlling the drain and source select transistors and the side word line transistors, and a block switch for connecting a global word line to word lines of the memory cell block in response to the block select signal.

Semiconductor memory device having a block decoder for preventing disturbance from unselected memory blocks

A page buffer circuit with reduced size and methods for reading and programming data is provided. In the reading operation, the page buffer circuit reads out a data bit by alternatively using a higher bit register or a lower bit register regardless of whether the data bit read from the multi-level cell is a higher bit or a lower bit, thereby reducing the circuit area and improves the performance of operation.

Page buffer circuit with reduced size and methods for reading and programming data with the same

A method of reading a nonvolatile memory device may include, after an nerase operation is performed, reading dummy cells on which a program operation has been performed based on a first read voltage, where n is an integer greater than zero, counting a number of dummy cells that are read as having a threshold voltage lower than the first read voltage, when the number is a critical value or more, resetting a read voltage, and performing, based on the reset read voltage, a read operation on memory cells that belong to the same memory cell block as the dummy cells and on which a program operation has been performed on the memory cells after the nerase operation has been performed.

Method of reading nonvolatile memory device and method of operating nonvolatile memory device

A page buffer circuit comprises a bit line selection unit, a latch unit, and a bit line control unit. The bit line selection unit is configured to select a bit line coupled to memory cells. The latch unit comprises a plurality of latch circuits. The plurality of latch circuits is coupled to a sense node and configured to latch data to be programmed into the memory cells or store data from the memory cells. The bit line control unit is coupled to the sense node and configured to temporarily charge a voltage of the selected bit line in response to charge and transfer control signals or transfer the charged voltage to the selected bit line.

Page buffer circuit, nonvolatile memory device including the page buffer circuit, and method of operating the nonvolatile memory device

A method for performing erasing operation in a nonvolatile memory device includes the steps of applying an erasing voltage to P-wells of a selected memory cell block which is composed of a plurality of strings in each of which a plurality of memory cells and side memory cells are connected in series; performing soft programming operation by applying a soft programming voltage to word lines of the selected memory cell block; and programming the side memory cells by applying a programming voltage to the side memory cells.

Growing community of inventors

Icheon-si, South Korea

Sam Kyu Won