Tru-si Technologies, Inc.

Nanosolar, Inc.

Sam Kao

Martin R Roscheisen

James R Sheats

Sergey Savastiouk

Patrick B Halahan

Oleg Siniaguine

Craig Leidholm

Brent Bollman

Patrick A Halahan

Gregory A Miller

Bosco Lan

A thin-film absorber formation method includes: operating a furnace having an internal atmosphere containing a process gas; loading process gas material into a source container that is part of a system configured to provide process gas to the furnace, wherein loading of the source container occurs without exposing the internal atmosphere of the furnace to external atmosphere present in the source container by solidifying process gas material to form a gas tight seal to separate the source container from the furnace, wherein the seal is formed before the source container is opened for loading and external atmosphere enters the source container, including a pathway configured to retain process gas material in a section of the pathway to solidify and create the seal.

Thin-film absorber formation method

Methods and devices are provided for absorber layers formed on foil substrate. In one embodiment, a method of manufacturing photovoltaic devices may be comprised of providing a substrate comprising of at least one electrically conductive aluminum foil substrate, at least one electrically conductive diffusion barrier layer, and at least one electrically conductive electrode layer above the diffusion barrier layer. The diffusion barrier layer may prevent chemical interaction between the aluminum foil substrate and the electrode layer. An absorber layer may be formed on the substrate. In one embodiment, the absorber layer may be a non-silicon absorber layer. In another embodiment, the absorber layer may be an amorphous silicon (doped or undoped) absorber layer. Optionally, the absorber layer may be based on organic and/or inorganic materials.

Formation of solar cells with conductive barrier layers and foil substrates

Optoelectronic device modules, arrays optoelectronic device modules and methods for fabricating optoelectronic device modules are disclosed. The device modules are made using a starting substrate having an insulator layer sandwiched between a bottom electrode made of a flexible bulk conductor and a conductive back plane. An active layer is disposed between the bottom electrode and a transparent conducting layer. One or more electrical contacts between the transparent conducting layer and the back plane are formed through the transparent conducting layer, the active layer, the flexible bulk conductor and the insulating layer. The electrical contacts are electrically isolated from the active layer, the bottom electrode and the insulating layer.

Optoelectronic architecture having compound conducting substrate

Photovoltaic devices with conductive barrier layers and foil substrates

Series interconnection of optoelectronic device modules is disclosed. Each device module includes an active layer disposed between a bottom electrode and a transparent conducting layer. An insulating layer is disposed between the bottom electrode of a first device module and a backside top electrode of the first device module. One or more vias are formed through the active layer, transparent conducting layer and insulating layer of the first device module. Sidewalls of the vias are coated with an insulating material such that a channel is formed through the insulating material to the backside top electrode of the first device module. The channel is at least partially filled with an electrically conductive material to form a plug that makes electrical contact between the transparent conducting layer and the backside top electrode of the first device module. Portions of the backside top electrode and insulating layer of a second device module are cut back to expose a portion of the bottom electrode of the second device module. The first and second device modules are attached to an insulating carrier substrate. Electrical contact is made between the backside top electrode of the first device module and the exposed portion of the bottom electrode of the second device module.

Series interconnected optoelectronic device module assembly

A through hole () is formed in a wafer () comprising a semiconductor substrate (). A seed layer () is sputtered on the bottom surface of the wafer. The seed is not deposited over the through hole's sidewalls adjacent the top surface of the wafer. A conductor () is electroplated into the through hole. In another embodiment, a seed is deposited into an opening in a wafer through a dry film resist mask (). The dry film resist overhangs the edges of the opening, so the seed is not deposited over the opening's sidewalls adjacent the top surface of the wafer. In another embodiment, a dielectric () is formed in an opening in a semiconductor substrate () by a non-conformal physical vapor deposition (PVD) process that deposits the dielectric on the sidewalls but not the bottom of the opening. A seed () is formed on the bottom by electroless plating. A conductor () is electroplated on the seed. In another embodiment, a dielectric () is formed in the opening to cover the entire surface of the opening. A non-conformal layer () is deposited by PVD over the sidewalls but not the bottom of the opening. The dielectric () is etched off the bottom with the non-conformal layer () as a mask. A seed () is formed on the bottom by electroless plating. The non-conformal layer can be formed by electroplating. It can be tantalum deposited by electroplating, then anodized. Other embodiments are also provided.

Electroplating and electroless plating of conductive materials into openings, and structures obtained thereby

Vias (B) are formed in a surface of a substrate. At least portions of contact pads () are located in the vias. Contact pads () of an integrated circuit structure are inserted into the vias and attached to the contact pads () of the substrate. The vias provide a strong, reliable mechanical and electrical connection. A via may expose not only a contact pad () in the substrate but also a surrounding region. Solder () wets the contact pad better than the surrounding region, resulting in a stronger solder joint and better electrical conductivity. Alternatively, the contact may include multiple conductive layers (), with the top layer () being more solder wettable than the bottom layer () and the top layer covering only a portion of the bottom layer.

Attachment of integrated circuit structures and other substrates to substrates with vias

A packaging substrate () includes a semiconductor interposer () and at least one other intermediate substrate (), e.g. a BT substrate. The semiconductor interposer has first contact pads (C) attachable to dies () above the interposer, and second contact pads () attachable to circuitry below the interposer. Through vias () are made in the semiconductor substrate () of the interposer (). Conductive paths going through the through vias connect the first contact pads (C) to the second contact pads (). The second contact pads () protrude on the bottom surface of the interposer. These protruding contact pads () are inserted into vias () formed in the top surface of the BT substrate. The vias provide a strong mechanical connection and facilitate the interposer handling, especially if the interposer is thin. In some embodiments, an interposer or a die () has vias in the top surface. Protruding contact pads () of another die () are inserted into these vias to provide a strong connection.

Integrated circuits and packaging substrates with cavities, and attachment methods including insertion of protruding contact pads into cavities

A packaging substrate () includes a semiconductor interposer () and at least one other intermediate substrate (), e.g. a BT substrate. The semiconductor interposer has first contact pads (C) attachable to dies () above the interposer, and second contact pads () attachable to circuitry below the interposer. Through vias () are made in the semiconductor substrate () of the interposer (). Conductive paths going through the through vias connect the first contact pads (C) to the second contact pads (). The dies () are attached to the interposer after the attachment of the interposer to the BT substrate. In sequential soldering operations, the solder hierarchy is maintained by dissolving some material (e.g. copper) in the solder during soldering to raise the solder's melting temperature. For example, all of the solders may initially have the same melting temperature, but each solder's melting temperature is increased during soldering to prevent the solder from melting in the subsequent soldering operations.

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San Mateo, CA, United States of America

Sam Kao