Samsung Electronics Co., Ltd.

Sam-jong Choi

Kyoo-chul Cho

Tae-soo Kang

Young-soo Park

Joon-Young Choi

Kyung-soo Kim

Jae-ryong Jung

Sang-Sig Kim

Tae-Hyoung Koo

Yong-kwon Kim

Jin-Ho Kim

Taesung Kim

Won-Joo Kim

Young-Soo Park

Kyoo-Chul Cho

Sang-Eun Lee

Sue-ryeon Kim

Gi-jung Kim

Hee-Sung Kim

Jong-soo Kim

Gi-Jung Kim

Kyoochul Cho

Sun-Ha Hwang

Yeonsook Kim

Hoe-Sik Chung

Joonyoung Choi

Ji-Won You

Heesung Kim

Tae-hyoung Koo

Shin-Hyeok Han

Hyun-hee Ju

Cheong-jun Kim

Yeon-Sook Kim

A semiconductor wafer including a main body including first and second surfaces opposite each other, a notch including a recess on an outer periphery, a first bevel region formed along the outer periphery of the main body, including a first slope connecting the first and second surfaces and having a first height with respect to a straight line extending from a first point where the first surface and the first slope meet to a second point where the second surface and the first slope meet, and a second bevel region in contact with the recess or opening, including a second slope connecting the first and second surfaces and having a second height, different from the first height, with respect to a straight line extending from a third point where the first surface and the second slope meet to a fourth point where the second surface and the second slope meet.

Semiconductor wafer, semiconductor structure and method of manufacturing the semiconductor wafer

A nonvolatile memory device includes a substrate, an elongate isolation region including a field insulation film disposed in a trench in the substrate, and a word line crossing the insulation region and including a tunneling insulation layer on an active region of the substrate adjacent the isolation region, a charge storage layer on the tunneling insulation layer and a blocking insulation layer on the charge storage layer. A first plane index of a bottom surface of the trench has a first interface trap density and a second plane index of a sidewall of the trench has a second interface trap density equal to or less than the first interface trap density. In some embodiments, the first plane index may be (100) and the second plane index may be (100) or (310).

Nonvolatile memory devices with aligned trench isolation regions

A three-dimensional (3D) CMOS image sensor (CIS) that sufficiently absorbs incident infrared-rays (IRs) and includes an infrared-ray (IR) receiving unit formed in a thin epitaxial film, thereby being easily manufactured using a conventional CIS process, a sensor system including the 3D CIS, and a method of manufacturing the 3D CIS, the 3D CIS including an IR receiving part absorbing IRs incident thereto by repetitive reflection to produce electron-hole pairs (EHPs); and an electrode part formed on the IR receiving part and collecting electrons produced by applying a predetermined voltage thereto.

3D CMOS image sensors, sensor systems including the same

A wafer, a fabricating method of the same, and a semiconductor substrate are provided. The wafer includes a first substrate layer formed at a first surface, a second substrate layer formed at a second surface opposite to the first surface, the second substrate layer having a greater oxygen concentration than the first substrate layer, and an oxygen diffusion protecting layer formed between the first substrate layer and the second substrate layer, the oxygen diffusion protecting layer being located closer to the first surface than to the second surface.

Wafer, fabricating method of the same, and semiconductor substrate

A method of processing a semiconductor wafer includes preheating the wafer to a preheating temperature that is less than a peak temperature, heating the wafer from the preheating temperature to the peak temperature at a first ramp rate that averages about 100&#xb0; C. per second or more, and, immediately after heating the wafer from the preheating temperature to the peak temperature, cooling the wafer at a second ramp rate that averages about &#x2212;70&#xb0; C. per second or more from the peak temperature to the preheating temperature, wherein the peak temperature is about 1,100&#xb0; C. or more.

Semiconductor wafer, semiconductor device using the same, and method and apparatus for producing the same

Methods of forming a gate structure for an integrated circuit memory device include forming a first dielectric layer having a dielectric constant of under 7 on an integrated circuit substrate. Ions of a selected element from group 4 of the periodic table and having a thermal diffusivity of less than about 0.5 centimeters per second (cm/s) are injected into the first dielectric layer to form a charge storing region in the first dielectric layer with a tunnel dielectric layer under the charge storing region. A metal oxide second dielectric layer is formed on the first dielectric layer, the second dielectric layer. The substrate including the first and second dielectric layers is thermally treated to form a plurality of discrete charge storing nano crystals in the charge storing region and a gate electrode layer is formed on the second dielectric layer. Gate structures for integrated circuit devices and memory cells are also provided.

Integrated circuit device gate structures

Provided are a semiconductor device, and a method of forming the same. In one embodiment, the semiconductor device includes a semiconductor layer, first and second semiconductor fins, an insulating layer, and an inter-fin connection member. The first and second semiconductor fins are placed on the semiconductor layer, and have different crystal directions. The first semiconductor fin is connected to the semiconductor layer, and has the equivalent crystal direction as that of the semiconductor layer. The insulating layer is interposed between the second semiconductor fin and the semiconductor layer, and has an opening in which the first semiconductor fin is inserted. The inter-fin connection member connects the first semiconductor fin and the second semiconductor fin together on the insulating layer.

Semiconductor device and method for forming the same

Methods of forming integrated circuit device gate structures

A semiconductor wafer including an identification indication is provided. The wafer includes a convex edge with an upper surface area and a lower surface area. The identification indication is in a marking region which is disposed on a lower side surface of the convex edge. The lower side surface has a wide region where the marking region is located. This wide region has a width that is wider than an upper side surface of the wafer and thus makes a cross-section of a side of the wafer asymmetrical. With the present invention, the entire top surface of the semiconductor wafer can be utilized for a semiconductor chip region and prevents manufacturing problems associated with the uneven nature of the identification indication when the identification is located on the top surface of the wafer.

Semiconductor wafer having identification indication

Growing community of inventors

Suwon-si, South Korea

Sam-jong Choi