Altera Corporation

Sam Hedinger

Robert L Pelt

Philip Clarke

Manoj Reghunath

An integrated circuit may be provided with system-on-chip circuitry including system-on-chip interconnects and a microprocessor unit subsystem. The subsystem may include microprocessor cores that execute instructions stored in memory. Cache may be used to cache data for the microprocessor cores. A memory coherency control unit may be used to maintain memory coherency during operation of the microprocessor unit subsystem. The memory coherency control unit may be coupled to the system-on-chip interconnects by a bus. A command translator may be interposed in the bus. The command translator may have a slave interface that communicates with the interconnects and a master interface that communicates with the memory coherency control unit. The integrated circuit may have programmable circuitry that is programmed to implement a debug master coupled to the interconnects. During debug operations, the command translator may translate commands from the debug master.

Cache debug system for programmable circuits

Memory controller circuitry may process the memory access requests by reordering the sequence of requests. Reordering the sequence of requests may decrease the power consumption of the memory controller and system memory associated with the memory controller. The memory controller may operate in at least an unconstrained power mode, a priority mode, and a constrained power mode. In the unconstrained power mode, the memory controller may process memory access requests at elevated and power consumption levels. In the priority mode, the memory controller may process memory access requests from select sources with reduced power consumption. In the constrained power mode, the memory controller may process all memory access requests at reduced power consumption levels. Capacitive-model based power monitoring circuitry may be used to monitor the interactions between the memory controller and the system memory to dynamically adjust the operating mode of the memory controller.

Power-aware memory controller circuitry

A bridge circuit may be used to interface between dynamically reconfigurable circuitry and dedicated circuitry or other circuitry having static configurations during normal operation of the device. The bridge circuit may include interface circuitry coupled between first and second interfaces that communicate with the dynamically reconfigurable circuitry and the dedicated circuitry. Control circuitry may control the interface circuitry based on variable communications requirements of the second interface without interrupting communications with the dedicated circuitry at the first interface. The variable communications requirements may be dependent on which configuration of the dynamically reconfigurable circuitry is currently implemented.

Bridge circuitry for communications with dynamically reconfigurable circuits

Methods and systems for AXI ID compression are disclosed. Bus transaction data and an M-bit ID associated with the bus transaction data are transmitted by a master device via a bus to an ID mapper. The ID mapper is used to select, based on the M-bit ID, an N-bit ID from a plurality of N-bit IDs, where N may be less than M. The N-bit ID is associated with the bus transaction data. The bus transaction data and the N-bit ID associated with the bus transaction data are transmitted via the bus to a slave device.

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Austin, TX, United States of America

Sam Hedinger