International Business Machines Corporation

Sam G Chu

Dung Q Nguyen

David R Terry

Saiful Islam

Steven J Battle

Eula A Tolentino

Owen Chiang

Hung Qui Le

Brian William Thompto

Jose Eduardo Moreira

Markus Kaltenbach

Jentje Leenstra

Peter Juergen Klim

Jose Angel Paredes

Michael J Lee

Joel Abraham Silberman

Mary Douglass Brown

Joshua W Bowman

Robert Allen Cordes

Maureen Anne Delaney

Cliff Kucharski

Dhivya Jeganathan

Jafar Nahidi

Binglong Zhang

Bjorn P Christensen

Howard Lawrence Levy

An approach is provided in which a system writes a set of data into a register file entry that includes a first memory array and a second memory array. The register file entry also includes a set of first write ports corresponding to the first memory array and a set of second write ports corresponding to the second memory array. The system configures a selection bit based on determining that a selected one of the set of first write ports is utilized to store the set of data in the first memory array. In turn, the system reads the set of data out of the first memory array based on the configured selection bit.

Implementing write ports in register-file array cell

Embodiments of the present invention provide systems and methods for mapping the architected state of one or more threads to a set of distributed physical register files to enable independent execution of one or more threads in a multiple slice processor. In one embodiment, a system is disclosed including a plurality of dispatch queues which receive instructions from one or more threads and an even number of parallel execution slices, each parallel execution slice containing a register file. A routing network directs an output from the dispatch queues to the parallel execution slices and the parallel execution slices independently execute the one or more threads.

Independent mapping of threads

Reducing power consumption in a multi-slice computer processor that includes a re-order buffer and an architected register file, including: designating an entry in the re-order buffer as being invalid and unwritten; assigning a pending instruction to the entry in the re-order buffer; responsive to assigning the pending instruction to the entry in the re-order buffer, designating the entry as being valid; writing data generated by executing the pending instruction into the re-order buffer; and responsive to writing data generated by executing the pending instruction into the re-order buffer, designating the entry as being written.

Reducing power consumption in a multi-slice computer processor

Methods and apparatus for preventing premature reads from a general purpose register (GPR) including receiving an instruction comprising a source operand identifying a source GPR entry; setting a read-enabled flag based on a value in a particular entry of a source ready vector; if the read-enabled flag indicates data in the source GPR entry is ready for reading, dispatching the received instruction, including performing a read operation of the data in the source GPR entry; and if the read-enabled flag indicates data in the source GPR entry is not ready for reading, dispatching the received instruction without performing a read operation of the data in the source GPR entry.

Preventing premature reads from a general purpose register

The embodiments herein generate parity check data which serves as parity-on-parity. Stated differently, the parity check data can be used to determine if parity data stored in a memory element has been corrupted. For example, after generating the parity data, a computing system may set the parity check data depending on whether there is an even or odd number of logical ones (or logical zeros) in the parity data. Thus, when the parity data is read out of the memory element, if the parity data does not include the same number of even or odd bits, the parity check data indicates to the computing system that the parity data is corrupted. In one embodiment, to reduce the likelihood that the parity check data becomes corrupted, the computing system stores this data in hardened latches which are less susceptible to soft errors than other types of memory elements.

Parity protection of a register

A processor having a dependency matrix comprises a first array comprising a plurality of first cells. A second array couples to the first array and comprises a plurality of second cells. A first write port couples to the first array and the second array and writes to the first array and the second array. A first read port couples to the first array and the second array and reads from the first array and the second array. A second read port couples to the first array and reads from the first array. A second write port couples to the second read port, reads from the second read port and writes to the second array.

Dependency matrix with reduced area and power consumption

A system and method of selective row energization based on write data, with a selective row energization system including a storage arrayhaving M rowsand N columns; an N-bit data word register; a uniform-detect circuitresponsive to a data word to generate a uniform word data bit having a first value when the data word is uniform; an M-bit uniform-detect registerhaving M uniform-detect latches, each being associated with one of the M rowsand storing the uniform word data bit for the data word stored in the associated M row; and an M-bit row driver deviceresponsive to the uniform word data bit for each of the M rowsto inhibit energization of the M rowsfor which the uniform word data bit is the first value.

System and method of selective row energization based on write data

Growing community of inventors

Round Rock, TX, United States of America

Sam G Chu