Arm Limited

The Chancellor, Masters and Scholars of the University of Cambridge

Sam Ainsworth

Thomas Christopher Grocutt

Timothy Gareth Jones

An apparatus comprises a main processor to execute a main stream of program instructions, two or more checker processors to execute respective checker streams of program instructions in parallel with each other, the checker streams corresponding to different portions of the main stream executed by the main processor, and error detection circuitry to detect an error when a mismatch is detected between an outcome of a given portion of the main stream executed on the main processor and an outcome of the corresponding checker stream executed on one of the plurality of checker processors. This approach enables high performance main processorsto be checked for errors with lower circuit area and power consumption overhead than a dual-core lockstep technique.

Main processor error detection using checker processors

A main processorexecutes a main program and has an associated cache memory. Event detection circuitrydetects events consequent upon execution of the main program and indicative of data to be used by the main processor. One or more programmable further processorsis triggered to execute a further program by the events detected by the event detection circuitry. Prefetch circuitryis responsive to the further program executed by the one or more programmable further processors to trigger prefetching of the data to be used by the main processor to the cache memory.

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Cambridge, United Kingdom

Sam Ainsworth