Synopsys, Inc.

Salvatore Talluto

Rohit Kapur

Frederic J Neuveux

Alodeep Sanyal

Girish A Patankar

Anubhav Sinha

Sorin Ioan Popa

Ramalingam Kolisetti

Amit Gopal M Purohit

Sai Manish Rao Marru

Sahil Soni

Andrea Costa

Leela Krishna Thota

A block of circuitry contains at least one sub-block. Test patterns for the sub-block (sub-level test patterns) include sub-level test stimuli and corresponding sub-level test responses. These are ported to the block-level to produce block-level test patterns, block-level test stimuli, and block-level test responses. The block-level test patterns are validated as follows. Propagation of the block-level test stimuli through the block-level design is computed. The signals produced by such computed propagation at the sub-block inputs are compared against the sub-level test stimuli, and the signals produced by such computed propagation at the block outputs are compared against the block-level test responses.

Validating test patterns ported between different levels of a hierarchical design of an integrated circuit

Techniques for testing an integrated circuit (IC) are disclosed. A controller in the IC retrieves first testing data from a first memory in the IC. The controller transmits the first testing data to a first built-in self-test (BIST) core. The controller receives a response from the first BIST core, relating to a test at the first BIST core using the first testing data. The controller determines a status of the test relating to the IC based on the response.

Packetized power-on-self-test controller for built-in self-test

Methods and apparatuses to assign faults to nets in an integrated circuit (IC) are described. Each net comprises a drive pin, a set of load pins, and a fan-out structure that electrically couples the drive pin to the set of load pins. During operation, a fan-out structure of a net can be partitioned into a set of non-overlapping subnets and a set of branch nodes, wherein each branch node electrically couples three or more non-overlapping subnets. Next, each branch node can be represented by using a subnet primitive, wherein each subnet primitive comprises three or more pins that are electrically coupled to non-overlapping subnets that are electrically coupled by the branch node. A fault can then be assigned to a pin of a subnet primitive that is electrically coupled to a non-overlapping subnet, thereby modeling the fault in the non-overlapping subnet.

Layout-aware test pattern generation and fault detection

A method for testing a design is provided. The method includes generating a sequence of bits, mapping the sequence of bits to a combination, and generating an enable signal based on the combination. The enable signal enables an asynchronous signal in the design. The method also includes driving an element of the design based on the enabled asynchronous signal.

Controlling clocks and resets in a logic built in self-test

Methods and apparatuses to generate test patterns for detecting faults in an integrated circuit (IC) are described. During operation, the system receives a netlist and a layout for the IC. The system then generates a set of faults associated with the netlist to model a set of defects associated with the IC. Next, the system determines a set of likelihoods of occurrence for the set of faults based at least on a portion of the layout associated with each fault in the set of faults. The system subsequently generates a set of test patterns to target the set of faults, wherein the set of test patterns are generated based at least on the set of likelihoods of occurrence associated with the set of faults.

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Cavanago di Brianza, Italy

Salvatore Talluto