Stmicroelectronics S.r.l.

Salvatore Poli

Paolino Schillaci

Salvatore Polizzi

Giovanni Carlo Tripoli

Antonino La Malfa

Maurizio Francesco Perroni

Matteo Quartiroli

Roberto Faravelli

Alessandro Tocchio

Marco Castellano

Antonio Giambartino

Pierluigi Montinari

Slavatore Polizzi

A method for compensating non-linearities of a read signal generated by a variable-capacitance inertial sensor including a first fixed electrode and a second fixed electrode and a mobile electrode, which is spatially arranged between the first and second fixed electrodes and is capacitively coupled to the first and second fixed electrodes, said method comprising the steps of: acquiring the read signal; identifying a first linear component and at least one first nonlinear component of the read signal; a generating a compensated output signal by subtracting the first nonlinear component from the read signal.

Method and system for compensating systematic non-linearities of a signal provided by a capacitive inertial sensor

One or more first signals and one or more second signals, wherein the second signal(s) are slowly varying or low frequency signals in comparison with the first signals and are converted from analog to digital by sampling the first signals and the second signals to produce samples thereof for analog-to-digital conversion, subjecting the samples of the first signals to conversion to digital at a certain conversion rate, subjecting the samples of the second signal to conversion to digital by segments so that these segments are subjected to conversion to digital along with the samples of the first signals at the respective conversion rate, and reconstructing digital converted samples of the second signal from the segments subjected to conversion to digital.

Method and a device for analog-to-digital conversion of signals, corresponding apparatus

Method and device for analog-to-digital conversion of signals, corresponding apparatus

The invention relates to an automatic decoding method for mapping and selecting a non-volatile memory device having a LPC serial communication interface in the available addressing area on motherboards. A logic structure is incorporated in the memory device, which allows a correct decoding to address the memory to the top of the addressable area or to the bottom of the same area, i.e., in both possible cases. This logic incorporates a non-volatile register whose information is stored in a Content Address Memory to enable the automatic mapping of the memory in the addressable memory area.

Automatic decoding method for mapping and selecting a non-volatile memory device having a LPC serial communication interface in the available addressing area on motherboards

The invention provides a protocol cycle during which a memory address and all the data bytes to be written are transmitted, and the writing process is carried out only once for all the transmitted data bytes, by writing a first byte in the memory sector corresponding to a first address generated by resetting to zero the 2 least significant bits of the transmitted address and all the other transmitted bytes in successive addresses. The method includes writing a certain number N of data bytes, in consecutive memory addresses in a memory array of a memory device, and includes unprotecting the memory sectors in which data are to be written, communicating the programming command to the memory device, communicating to the memory device the bits to be stored and specifying a relative memory address of a sector to write in, and writing the data bits in the memory.

Method of writing a group of data bytes in a memory and memory device

The invention relates to a method for testing non-volatile memory devices that have at least one parallel communication interface, and a conventional matrix of non-volatile memory cells with respective reading, changing and erasing circuits, wherein during the testing procedure, a reading mode is entered for reading a memory location upon the rise edge of a control signal producing a corresponding ATD signal. Advantageously in the invention, a subsequent reading step is started also upon the fall edge of the control signal. In this way, at each cycle of the control signal two memory locations, instead of one as in the prior art, are read.

Device and method for reading non-volatile memories having at least one pseudo-parallel communication interface

An electronic circuit structure for updating a block of memory cells in a flash memory device, the memory cells storing a current value, wherein the structure includes a data latch for receiving a new value to be written on the memory cells, a controller for erasing the block of memory cells simultaneously, and programming load bank coupled to the controller and the data latch for programming the memory cells individually; the structure further includes control logic coupled to the controller for enabling the controller and for enabling the programming load bank according to a comparison between the new value and the current value.

Structure for updating a block of memory cells in a flash memory device with erase and program operation reduction

A nonvolatile memory device is operable in a serial mode and in a parallel mode. The architecture of the nonvolatile memory device is based upon the structure already present in a standard memory, but includes certain modifications. These modifications include the addition of a timing state machine for the various memory access phases (i.e., writing and reading data), and the addition of an internal bus and related logic circuits for disabling the internal address bus of the standard memory when the nonvolatile memory device operates in the serial mode.

Nonvolatile memory device with double serial/parallel communication interface

A circuit architecture and a method perform a page programming in non-volatile memory electronic devices equipped with a memory cell matrix and an SPI serial communication interface, as well as circuit portions associated to the cell matrix and responsible for the addressing, decoding, reading, writing and erasing of the memory cell content. Advantageously, a buffer memory bank is provided to store and output data during the page programming in the pseudo-serial mode through the interface. Data latching is performed one bit at a time and the following outputting occurs instead with at least two bytes at a time.

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Mascalucia, Italy

Salvatore Poli