International Business Machines Corporation

Jds Uniphase Corporaton

Salvatore Nicholas Storino

Gregory John Uhlmann

Jeff Van Tran

Andrew Douglas Davies

Robert Russell Williams

Leland Chang

Robert K Montoye

Todd Alan Christensen

William Paul Hovis

Phil Christopher Paone

Anthony Gus Aipperspach

Steven John Baumgartner

George Francis Paulik

Gary S Ditlow

David W Siljenberg

Stephen J Ames

Nghia Van Phan

Michael James Rohn

Jerry C Kao

Chihhung Liao

Peder James Paulson

Alan James Leslie

Christophe Robert Tretz

Binta Minesh Patel

Brian Joy Reed

Chun-Tao Li

Phu Nguyen

Eugene E Distad

Bart Owen McCoy

Vimal Ramannhai Patel

Mankit Wong

Bryan Joe Talik

Chung-Tao Li

Michael Joseph Connell, Iii

An eFuse circuit may include a wordline, a first eFuse, a first logic gate, a first blowFET, and a first bitline discharge device. The first eFuse may have a first end coupled to the wordline and a second end. The first eFuse may have a first resistance when unblown and a second resistance when blown. The first logic gate may be coupled to the first end of the first eFuse. The first logic gate may be capable of driving enough current to blow the first eFuse. The first blowFET may have a source coupled to a first supply voltage, a gate coupled to a program signal, and a drain coupled to the second end of the first eFuse. The first bitline discharge device may have a gate coupled to the second end of the first eFuse, a source coupled to the first supply voltage, and a drain coupled to a first bitline.

State sensing system for eFuse memory

An embodiment of the invention provides a method of separating an early clock pulse and a late clock pulse into two different latches, wherein the early clock pulse is generated through a bit line. In response to the early clock pulse rising, a first data waveform is sent to a fourth data waveform. In response to a third data waveform rising, an early precharge is turned off. In response to the turning off of the early precharge and in response to a fifth data waveform dropping, an eighth data waveform rises if the first data waveform has a value of 1. In response to a sixth data waveform rising, a first pulse latch is opened.

SerDes double rate bitline with interlock to block precharge capture

Disclosed is a metal fill region of a semiconductor chip including a plurality of layer sets of the semiconductor chip, each set including a first metal fill layer, a second metal fill layer, and an insulation layer included disposed in planes parallel to each other, a plurality of metal fill pieces disposed in each of the metal fill layers, a metal fill piece axis of each of the pieces, wherein each of the axes perpendicularly intersects the planes of said metal fill layers and the insulation layer from any point of reference, and a metal fill pattern configured to position the pieces so that the axis of each piece in the first metal fill layer is linearly displaced of the axis of each piece in the second metal fill layer in at least one direction orthogonal to each of the metal fill axes.

Metal fill region of a semiconductor chip

A method and apparatus are provided for implementing subthreshold leakage current reduction in limited switch dynamic logic (LSDL). A limited switch dynamic logic circuit includes a cross-coupled NAND and inverter logic. A dynamic node provides a first input to the NAND. A sleep signal provides a second input to the NAND. An output of the NAND provides an input to the inverter logic that inverts the NAND output and provides a complementary output. The NAND logic includes a series connected first sleep transistor receiving the sleep input. The first sleep transistor is turned OFF during the sleep mode. A second sleep transistor is connected between a voltage supply rail and the NAND output. The second sleep transistor is turned ON during the sleep mode to force high the NAND output and force low complementary output.

Method and apparatus for implementing subthreshold leakage reduction in LSDL

An eFuse reference cell on a chip provides a reference voltage that is greater than a maximum voltage produced by an eFuse cell having an unblown eFuse on the chip but less than a minimum voltage produced by an eFuse cell having a blown eFuse on the chip. A reference current flows through a resistor and an unblown eFuse in the eFuse reference cell, producing the reference voltage. The reference voltage is used to create a mirrored copy of the reference current in the eFuse cell. The mirrored copy of the reference current flows through an eFuse in the eFuse cell. A comparator receives the reference voltage and the voltage produced by the eFuse cell. The comparator produces an output logic level responsive to the voltage produced by the eFuse cell compared to the reference voltage.

eFuse sense circuit

A wireless data retrieval device and method for implementing the same. In accordance with one embodiment of the invention, the wireless data retrieval device includes a first-in-first-out (FIFO) memory queue in the form of a linked list that stores standardized correspondence information. The wireless data retrieval device further includes an input/output device configured to transmit the standardized correspondence information to and receive said standardized correspondence information from a wireless channel.

Method and apparatus for simplified data dispensation to and from digital systems

Techniques and circuits for generating a pair of differential signals with balanced switching between logical states from a single ended input signal are provided. The differential signals may be generated by controlling the switching of substantially identical driver stages with a set of control signals generated based on the single ended input signal.

Balanced single ended to differential signal converter

The present invention is an apparatus and method for eliminating parasitic bipolar transistor action in a Silicon on Insulator (SOI) Metal Oxide Semiconductor (MOS) device. In accordance with the invention a SOI electronic device and an active discharging device coupled to said SOI electronic device is provided to deactivate the parasitic bipolar transistor. The parasitic bipolar transistor action is deactivated by controlling the conduction of an active discharging device, said active discharging device being coupled to said SOI device.

Method for elimination of parasitic bipolar action in silicon on insulator (SOI) dynamic logic circuits

A method and apparatus are described which periodically sense environmental conditions, such as temperature, humidity, or voltage applied to a product, and apply these sensed measurements to models of ageing acceleration. Acceleration factors from the models are accumulated in nonvolatile storage. The accumulated effective aging of the product is displayed to the owner or prospective customer in various desired formats, such as effective age, current acceleration factor, estimate of effective life used, or estimate of remaining life left in the product. A warning can be sent to the user to indicate that the product's effective life is over or is nearly over.

Method and apparatus for estimating remaining life of a product

In a multithreaded processor, a method and an apparatus to selectively disable one or more threads is disclosed. As multithreading is increasingly becoming the normative paradigm of computer architecture, there still may instances which warrant disabling a thread, such as using operating systems not coded for the specific number of threads, having defective registers/arrays peculiar to a thread, certain kinds of testing procedures. Thus a method is disclosed to test the function of each thread separately and discern if any threads have defective register/arrays. If so or for other reasons, a method and apparatus are disclosed to selectively disable access to the registers/arrays peculiar to the thread. Features of the invention allow the disablement of individual storage elements in multithreaded registers/arrays or to disable access to hardware registers or individual bits in hardware registers associated with the failed thread. Techniques can be used to route data and instructions for the disabled thread to other threads. Preferably, the tests are performed and the method to disable access to the register/arrays are accomplished before the processors are sold.

Changing the thread capacity of a multithreaded computer processor

A method, apparatus, and a program product to protect against thread loss in a multithreaded computer processor. The processor may experience the failure of one or more threads; in accordance with the invention, a functional test can be run to determine which thread is experiencing the failure. If the thread failure results the failure of a register/array that is uniquely associated with the thread, then the invention will disable access to those register/arrays. Each thread may have its own set of register/arrays or it may be uniquely assigned to one of a plurality of storage elements in a multithreaded register/array. Using this invention, a processor may continue processing other threads and the instructions and data associated with the disabled or defective thread can be rerouted.

Field protection against thread loss in a multithreaded computer processor

A flex cable has a number of conductive wirings for electrically coupling electrical leads of an electrical component to a wiring board. The flex cable has a conductive tab for electrically coupling one of the conductive wirings to one of the leads. The flex cable is bendable to form an essentially horizontal portion and an essentially vertical portion. The conductive tab is disposed at a transition between the horizontal portion and the vertical portion.

Enhanced flex cable

A circuit and a method to realize a programmable delay between two adjacent signal paths, each having a different timing domain. In a preferred embodiment, each signal path is a stage of domino logic and the programmable delay is positioned at the boundary to adjust the timing between the two stages. The delay is programmed depending upon the value of an input signal to be either a static delay and hence part of the first stage of domino logic; or a dynamic delay to be part of a subsequent stage of domino logic. Critical paths can easily be balanced after fabrication, either at wafer test or once the circuit is mounted on an integrated chip and then tested, with the programmable gate as disclosed herein.

Programmable timing boundary in dynamic circuits

Method and apparatus for elimination of parasitic bipolar action in complementary oxide semiconductor (CMOS) silicon on insulator (SOI) circuits

The present invention is an apparatus and method to overcome the unwanted effects of parasitic bipolar discharge in silicon-on-insulator (SOI) field effect transistors (FET) by expanding a stack SOI MOS devices arranged to provide a predetermined logic function. The SOI MOS devices are arranged so as to eliminate electrical connections between certain intermediate nodes of the dynamic logic circuit. Accordingly, eliminating any parasitic bipolar current leakage paths associated with such electrical connections between certain intermediate nodes of said stacked SOI MOS devices of said dynamic circuit.

Method and apparatus for elimination of parasitic bipolar action in logic circuits including complementary oxide semiconductor (CMOS) silicon on insulator (SOI) elements

Growing community of inventors

Rochester, MN, United States of America

Salvatore Nicholas Storino