Stmicroelectronics S.r.l.

Salvatore Mazzara

Maurizio Francesco Perroni

Salvatore Polizzi

Giuseppe Castagna

Paolino Schillaci

Salvatore Imbesi

A driving circuit is for an output buffer stage, with high speed and reduced noise induced on the power supply. The driving circuit may include first and second circuit portions, each intended for the generation of a respective driving signal for a corresponding transistor of the buffer stage. Each portion may include a final stage with a complementary pair of MOS transistors inserted between two supply voltage references, and a third MOS transistor having its conduction terminals connected between one of the voltage references and an interconnection node of the complementary pair and receiving, on its control terminal, an activation pulse signal coming from a logic network incorporating at least one delay chain.

Driving circuit of an output buffer stage having a high speed and a reduced noise induced on power supply

An integrated device is provided that includes a non-volatile memory having an addressing parallelism and a data parallelism, and a communication interface for interfacing the memory with an external bus. The external bus has a transfer parallelism lower than the addressing parallelism and the data parallelism. The communication interface includes control means for executing multiple reading operations and/or multiple writing operations on the memory according to different modalities in response to corresponding command codes received from the external bus. Also provided is a method of operating such an integrated device.

Integrated device with multiple reading and/or writing commands

A synchronous non-volatile memory device that includes a circuit for performing operations on the memory device, a circuit for receiving a request of operation and operative information required for performing the operation in temporal succession, an activation circuit for activating the circuit in response to the request of operation, a circuit for enabling the execution of the operation in response to the operative information, and a deactivation circuit for deactivating the operations performing circuit in response to the completion of the operation.

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Palermo, Italy

Salvatore Mazzara