Synopsys, Inc.

Salvatore Maria Amoroso

Victor Moroz

Plamen A Asenov

David Thomas Reid

Jaehyun Lee

Manuel Aldegunde Rodriguez

Binjie Cheng

Andrew John Pender

Andrew R Brown

A configuration to isolate ion implantation of silicon channels for placement of integrated circuit devices within an integrated circuit layout. The configuration layers a photolithographic mask having one or more openings on a silicon substrate. The configuration directs a focused ion beam towards the silicon substrate to implant ions in the silicon substrate at the one or more openings in the photolithographic mask. The configuration anneals the silicon substrate with the layered photolithographic mask to activate a reaction between silicon of the silicon substrate and the implanted ion to achieve an ionized formation in the silicon substrate.

Isolating ion implantation of silicon channels for integrated circuit layout

A method of forming a multitude of vertical NAND memory cells, includes, in part, forming a multitude of insulating materials on a silicon substrate, forming a trench in the insulating materials to expose a surface of the silicon substrate, depositing a layer of polysilicon along the sidewalls of the trench, filling the trench with oxide, forming a metal layer above the trench, and forming a mono-crystalline channel for the NAND memory cells by applying a voltage between the silicon substrate and the metal layer to cause the polysilicon sidewalls to melt. The melted polysilicon sidewalls is enable to recrystallize into the mono-crystalline channel.

Electro-thermal method to manufacture monocrystalline vertically oriented silicon channels for three-dimensional (3D) NAND memories

The design of Dynamic Random Access Memory (DRAM) pass transistors is provided via generating a first plurality of transistor leakage currents by simulating different dopant configurations in a transistor; generating a second plurality of transistor leakage currents by simulating, for each dopant configuration of the different dopant configurations, a single trap insertion in the transistor; fitting the first and second pluralities of transistor leakage currents with first and second leakage current distributions; combining the first and second leakage current distributions to produce a third leakage current distribution; generating a third plurality of statistically generated leakage currents for a specified trap density for the transistor based on the first leakage current distribution, on the second leakage current distribution and on a specified trap density; and modeling and evaluating a DRAM cell including the transistor based on the third plurality of statistically generated leakage currents.

Dynamic random-access memory pass transistors with statistical variations in leakage currents

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Hamilton, United Kingdom

Salvatore Maria Amoroso