Texas Instruments Corporation

Salvatore Luciano Finocchiaro

Baher S Haroun

Swaminathan Sankaran

Siraj Akhtar

Gerd Schuppener

Tolga Dinc

Timothy M Schmidl

Tolga Dine

Anand Ganesh Dabak

Francesco Dantoni

In described examples, a method of operating a charge pump includes a first control signal deactivating a first transistor, and the first control signal's logical complement activating a second transistor to reset the first transistor's DC bias voltage. The first control signal's logical complement deactivates the second transistor, and the first control signal provides a bias voltage to the first transistor to activate it, causing current to be transmitted from an input voltage to an output terminal. A second control signal deactivates a third transistor, and the second control signal's logical complement activates a fourth transistor to reset the second transistor's DC bias voltage. The second control signal's logical complement deactivates the fourth transistor, and the second control signal provides a bias voltage to the third transistor to activate it, causing current to be transmitted from the output terminal to a ground.

Charge pump

In described examples, a method of operating a transceiver with a transmitter and a receiver includes generating a frequency reference. In the transmitter: A phase locked loop (PLL) generates a first voltage controlled oscillator (VCO) control voltage responsive to the frequency reference. A VCO in the transmitter generates a transmitter VCO signal responsive to the first VCO control voltage, and the PLL is locked to the transmitter VCO signal. In the receiver: A signal is received. A receiver VCO generates a receiver VCO signal responsive to the first or a second VCO control voltage. The receiver VCO signal is multiplied by the received signal to generate an I component, and by the received signal phase shifted by 90&#xb0; to generate a Q component. The second VCO control signal is generated responsive to the I component and the Q component.

Transceiver carrier frequency tuning

Methods, apparatus, systems and articles of manufacture are disclosed to provide phase imbalance correction. An example system includes a phase detector to obtain a first signal and generate a first output, a comparator coupled to the phase detector, the comparator to generate a second output based on the first output, and an amplifier coupled to the comparator, the amplifier to adjust a first phase response of the first signal based on the second output.

Methods and apparatus for phase imbalance correction

In described examples, a method of operating a transmitter includes generating a frequency reference signal having a reference frequency and outputting the frequency reference to a phase locked loop (PLL) that includes a voltage controlled oscillator (VCO). The VCO output is locked to the frequency reference signal to form a carrier signal. The transmitter receives an I input signal, a Q input signal, and a direct current (DC) leaky carrier signal. Either the I input signal or the Q input signal is added to the leaky carrier signal. The carrier signal is modulated with the resulting two signals using an I-Q mixer to generate a modulated signal that includes an unmodulated carrier signal component. The modulated signal is then transmitted.

Carrier frequency recovery in a receiver

In many types of wireless applications (like wireless modems), it is important that the phase locked loops (PLLs) be able to synthesize clock frequencies in a wide tuning range. Because of the complexity of many conventional PLLs (which were deigned to cover wide tuning ranges), there was often a significant delay to achieve phase and frequency lock. Here, an open loop calibration system is provided to coarse tune a PLL very rapidly. Generally, this calibration system employs binary searches to coarsely adjust a voltage controlled oscillator (VCO) from a VCO bank to within a predetermined range around a target frequency.

Open loop coarse tuning for a PLL

An active RC filter () includes a first resistive element () and a first capacitor array () which co-acts with the first resistive element () to determine a bandwidth characteristic of the programmable active RC filter circuit (). The total filter capacitance is programmed by switching various first capacitors (-) of a first capacitor array () in parallel between first and second terminals of the first capacitor array in response to a control word (B) to determine a first portion of the bandwidth characteristic, and by switching various second capacitors (-) of the first capacitor array between the first and second terminals of the first capacitor array in parallel with various ones of the first capacitors (-) of the first capacitor array () in response to less significant bits (B) of the control word (B) to determine a second portion of the bandwidth characteristic.

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Dallas, TX, United States of America

Salvatore Luciano Finocchiaro