Data General Corporation

Salvatore Faletra

Stephen A Caldara

Louis A Lemone

Edward Gershenson

John R McDaniel

Mark C Lippitt

William A Braun

Steve A Caldara

Kenneth S Goekjian

Lou Lemone

John E Shur

Donald J Barbarits

A data processing system is disclosed in which a plurality of high performance, intelligent, mass storage input-output devices are linked to a host controller by an input-output interface bus which is divided into three sections. Each section is completely independent of the other two sections and used for a different and specific purpose. One section is used to transfer commands and retrieve status information. A second section is used to handle device requests for data transfer and device signals for operation complete. The third section is used to transfer data to and from a device. Since the three sections are completely independent, simultaneous transfer of command control and data to different input-output devices or to a single input-output device can be performed.

Interface bus with independent data, command and direct control sections

The disclosure relates to a memory mapping system wherein information is stored on a page by page basis in memory in discontiguous locations therein with the address of the next page in which storage is to take place always being available in the controller to minimize delay in storage from the end of one page to the beginning of the following page, regardless of page location in memory. When a user makes a request for storage space in memory, the amount of memory required is determined and the host looks to see where it can obtain that memory. Typically, use of discontiguous memory locations is required. All of the information relative to the addresses of the discontiguous storage locations in memory is provided to the controller by the host computer in a single command rather than after each move to a discontiguous storage location. All jumps to discontiguous storage locations are then performed independent of the host computer.

Memory mapping system

A digital data bus system for connecting a controller and a disk drive. Data on the disk is stored in track sectors containing a header and data. The controller includes a high-speed processor which performs a header compare operation comparing the values received from a header with the expected contents of the header and operations which determine when all of the data in a track sector has been transferred. The digital data bus system includes a bus for transferring data between the controller and the disk drive and a header-data mode bus for providing a header mode signal and a data mode signal from the controller to the disk drive. During an operation transferring data between the controller and the disk, the disk drive responds to the header mode signal by transferring a header to the controller. If the header compare operation indicates that the header is valid, the controller provides the data mode signal and the disk drive respond by transferring data to or from the track sector as required for the operation. When the controller determines that all of the data has been transferred, it again provides the header mode signal to the disk drive and the disk drive responds as just described.

Digital data bus system for connecting a controller and disk drives

Apparatus in a disk drive connected by separate buses to two controllers for suspending the effect of a reserve instruction received from one controller when the other controller has already reserved the disk drive until the other controller releases the disk drive. The apparatus corresponding to each controller consists of suspended reserve logic and a register for retaining state indicating whether the controller has reserved the bus and state indicating whether the reserve operation has been suspended for the controller. The suspended reserve logic for a given controller receives inputs from the controller's bus, from the state stored in its register, and from the state in the suspended reserve apparatus for the other controller indicating whether that controller has reserved the disk drive. Outputs from the suspended reserve logic go to its register. If the suspended reserve logic receives a reserve instruction when the state received from the other suspended reserve apparatus indicates that the other controller has reserved the disk drive, the suspended reserve logic sets the state indicating that the reserve operation has been suspended.

Apparatus for suspending a reserve operation in a disk drive

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Framingham, MA, United States of America

Salvatore Faletra