General Electric Company

Salvatore F Nati, Jr

Charles W Eichelberger

James F Bedard

Scott E Cutler

Edward B Miller

Christopher E Marchant

Young K Chen

David C Dening

The decoder herein described recovers the clocking and the data in a binary format from a three level coded signal. The decoder has application to data rates in excess of one half gigabits per second, which are common to optical communication channels. The decoder employs a comparator for evaluating to two bit accuracy each state of the signal, a two stage, two bit per stage shift register, and decision logic for recovering the data in a binary format. The decoder is monolithically integrated using buffered FET logic on a gallium arsenide substrate. In the decoder, the comparator is optimized by the use of three zero crossing detectors, one of which has a zero input for reference purposes, in combination with two internal voltage dividers and two external voltage references for achieving an accurate drift free determination of the levels of the three level code (TLC) signal. The clock recovery means is optimized for high speed operation by the use, in association with each transition level, of a time delay and an exclusive OR-gate, the logical design of the exclusive OR-gate entailing a four NOR-gate configuration in which the timing indication resulting from each TLC transition is propagated through a like number of states and thereby experiences the same overall propagation delay, in reaching the decoder output.

Decoder for three level coded data

A circuit, for providing a periodic signal of programmably controllable amplitude, includes an oscillator having a substantially constant amplitude signal of desired frequency and waveform at an output thereof connected to the input of a first programmable voltage divider having its output connected to one input of an operational amplifier. The remaining operational amplifier input is connected to the output thereof via a second programmable voltage divider used as a programmably controllable feedback network. The operational amplifier output signal amplitude may be controlled by external data signals to values less than, equal to, and greater than, the substantially constant oscillator waveform amplitude. Both computer and hard-wired circuitry for controlling the output signal are disclosed. An isolation-and-rectification network may be used to recover a D.C. voltage of programmably controlled amplitude.

Programmable signal amplitude control circuits

A control module for controlling at least one variable-power-consuming load responsive to data input from local and/or remote locations, utilizes a controller microcomputer having an output setting the gain of a variable gain amplifier. The variable gain amplifier operates on a substantially-constant output of an oscillator to provide, on a cycle-by-cycle or long-term basis, a periodic waveform of controlled amplitude to the at least one load. The amplitude of the waveform sets the energy consumption/output of the load. Another data bus facilitates connection of local control means to a control module interface providing local control information to the controller microcomputer, while a third data bus is dedicated to communication with a remote central controller, if used. The control module includes circuitry for allowing a unique local address to be set for a particular control module, to which unique address the control module responds when a plurality of such control modules are connected in parallel to a central controller. A fourth data bus connects local sensors, such a photocells, thermistors and the like, through analog-to-digital conversion circuitry to the controller microcomputer, to facilitate control of the local loads responsive to local ambient conditions. The maximum level of the load(s) connected to a control module may be programmably established such that this maximum level can not be exceeded by local and/or remote commands, until the maximum level is altered.

Control module for engergy management system

Circuits for providing a variable-amplitude D.C. analog control signal to a load, responsive to the time duration of a periodic, variable-pulse-width input signal, while providing isolation between the input signal circuit and the load circuit. Embodiments utilizing either a fly-back transformer or an optoelectronics isolator, are disclosed.

Control signal and isolation circuits

A circuit, for controlling the output level of a load circuit connected thereto, has a single input for receiving a control signal to provide both a selectable level on/off output signal at a first output connected to an on/off terminal of the load circuit, and a pair of essentially equal control currents drawn in shunt from a pair of output terminals connected to load output-level-setting input terminals. The shunt control currents are provided by a current-mirror circuit having a pair of substantially identical current sinks, each responsive to an input signal applied thereto in parallel from the single control circuit input.

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Syracuse, NY, United States of America

Salvatore F Nati, Jr