Crystal Semiconductor Corporation

Salvador R Bernadas

Michael Vayden Jenkins

Charles D Thompson

Qiujie Dong

Eric J Swanson

Nicholas R Van Bavel

The present invention relates to a tone signal generator. The tone signal generator includes first tone signal generation means for producing a dual-tone, multi-frequency ('DTMF') audio signal; second tone signal means for producing a plurality of non-DTMF audio signals; storage means for storing data that represents at least one channel of an output audio tone signal; and selection means for selectively loading the DTMF signal into the storage means and for selectively accumulating the non-DTMF signals into the storage means so as to generate the output tone signal.

Tone signal generator for producing multioperator tone signals

A frequency modulation (FM) tone signal generator for generating a FM tone signal is disclosed. The tone signal generator includes a waveform generator having a plurality of wave tables, a selector and an enveloper. The waveform generator furnishes a waveform signal in response to a phase angle address signal. Each wave table stores a different waveform. The selector selects one of the wave tables in response to a plurality of selection signals such that the selected wave table largely provides the waveform signal upon being addressed largely by the phase angle address signal. Selection of the selected wave table varies with each selection signal. The enveloper impresses an envelope signal on the waveform signal. The envelope signal is used as a carrier or modulator for generating the FM tone signal.

Tone signal generator for producing multioperator tone signals using an

A calibration method and apparatus to calibrate for non-linearities in a multi-level delta-sigma modulator (12) includes a calibration multiplexer (10) on the input for selecting in a calibration mode a zero voltage for input to the delta-sigma modulator (12). The delta-sigma modulator (12) has three levels, +1, 0, -1, the +1 level input to a processor (32) and the -1 level input to a processor (34). The processor (34) has the output thereof input to an compensation circuit (14) that offsets the value generated by the -1 processor (34) by a coefficient .delta.. The output of the compensation circuit (14) is then input to the minus input of a summation junction (36), which also receives the output of the processor (32), the output of summation junction (36) providing the digital output. The processors (32) and (34) are realized with a separate accumulator that switches between an associated filter coefficient and ground, the filter coefficient stored in a ROM (35). The .delta. coefficient is stored in a block (16) and is generated during a calibration cycle by a .delta. processor (39). The .delta. processor (39) receives the output of the compensation circuit (14) and the digital output from the summing junction (36) when the calibration multiplexer (10) sets the input to zero. A control circuit (40) controls the overall operation, with the calibration operation initiated in response to either an external signal on a line (30) or an internally generated signal. After calibration, the value of the .delta. coefficient is frozen and the calibration multiplexer (10) selects the analog input.

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Austin, TX, United States of America

Salvador R Bernadas